Lead Verification(PCIe-CXL) Engineer

Cadence System Design and Analysis; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Cadence System Design and Analysis seeks an experienced design verification professional for the IP development team in Bengaluru (with Noida as backup). You will verify Serial and Interface Design IPs (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C) using UVM testbenches and possibly formal verification, plus emulation qualification.

The role requires 5+ years of relevant experience, strong problem-solving and communication skills, and the ability to work across geographies

Qualifications

• B.Tech/M.Tech with 5+ years of relevant experience.
• Design verification for IP development team.
• Based in Bangalore/Noida; preference for Bangalore.
• Verify Serial and Interface Design IPs (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C).
• Develop UVM testbenches; may involve formal verification and emulation qualification.
• Produce detailed verification strategy and test plan.
• Demonstrate self-starting attitude and quality focus.
• Strong problem solving, debugging, and analytical skills.
• Excellent verbal and written communication; presentation skills.
• Ability to work across functions and geographies; collaborate with customers and management.
• Explore unconventional solutions to get the job done with integrity.

Responsibilities

• Design verification for IPs across PCIe, USB, Ethernet, and more.
• Develop robust UVM testbenches and verification environments.
• Perform formal verification as needed and assist in emulation qualification.
• Create verification strategy and detailed test plans.
• Communicate findings clearly to teams and customers.
• Collaborate across locations and teams to ensure on-time delivery.

Skills

IP verification

Self-starter

Team collaboration

Problem solving

Verbal communication

Written communication

Presentation skills

Analytical skills

Education

B.Tech / M.Tech in relevant field

Tools

UVM

Emulation qualification

Formal verification

Testbench development

Job description

• Design Verification role for IP development team.
• B. Tech/M.Tech with 5+ years of relevant experience.
• Position is based in Bangalore/Noida, part of Cadence IP Group.-> Preferred location is Bangalore.
• Verification role for Serial and Interface Design IPs verification (PCIe, CCIX, CXL, USB, Ethernet, SATA/SAS, UFS, SPI, HDMI, MIPI, I3C)
• UVM testbench development to build a robust, scalable and efficient testbench to verify the design IPs.
• In addition to UVM functional verification, role could involve Formal verification of complex design modules.
• In addition to UVM functional verification, role could involve participating in Emulation qualification of design IPs.
• Understand design and produce detailed verification strategy and test plan.
• Self-starter and learner with passion for getting the job done on time with great quality.
• Strong problem solving, analytical and debug skills
• Excellent verbal and written communications skills
• Must possess strong written, verbal and presentation skills.
• Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity