Lead Physical Design (PnR) Engineer

LanceSoft, Inc.; Chennai District; On-site; INR 5,000,000 - 8,000,000; Full time

Job summary

LanceSoft, Inc. in Chennai is seeking a Lead Physical Design (PnR) Engineer with 8+ years of experience to own end-to-end physical design from floorplanning to signoff. You will drive floorplanning, placement, CTS, routing, and timing closure, collaborate with RTL/STA/DFT teams, and lead debugging and optimization of full-chip designs using Cadence Innovus.

The role requires strong problem-solving and technical leadership to deliver tightly-timed silicon in a fast-paced hardware environment.

Qualifications

• 8+ years of experience in Physical Design / Place and Route (PnR).
• Strong hands-on experience with Cadence Innovus.
• Expertise in floorplanning, placement, CTS, routing, and timing closure.
• Strong knowledge of STA, power optimization, congestion analysis, and physical design signoff.
• Experience with advanced-node designs and full-chip implementation.
• Strong debugging, problem-solving, and technical leadership skills.

Responsibilities

• Lead end-to-end physical design implementation from floorplanning to signoff.
• Drive floorplanning, placement, CTS, routing, and physical optimization.
• Perform timing closure, congestion analysis, and power optimization.
• Handle physical design challenges and resolve complex timing and design issues.
• Collaborate with RTL, STA, DFT, and Physical Verification teams.

Skills

Physical Design

Cadence Innovus

Floorplanning

Placement & Routing

Timing Closure

Power Optimization

Leadership

Tools

Cadence Innovus

Job description

Job Title: Lead Physical Design (PnR) Engineer

Experience: 8+ Years

Job Description:

We are looking for an experienced Lead PnR Engineer with strong expertise in physical design implementation and hands-on experience with Cadence tools.

Key Responsibilities:

• Lead end-to-end physical design implementation from floorplanning to signoff.
• Drive floorplanning, placement, CTS, routing, and physical optimization.
• Perform timing closure, congestion analysis, and power optimization.
• Handle physical design challenges and resolve complex timing and design issues.
• Collaborate with RTL, STA, DFT, and Physical Verification teams.

Must-Have Skills:

• 8+ years of experience in Physical Design / Place and Route (PnR).
• Strong hands-on experience with Cadence Innovus.
• Expertise in floorplanning, placement, CTS, routing, and timing closure.
• Strong knowledge of STA, power optimization, congestion analysis, and physical design signoff.
• Experience with advanced-node designs and full-chip implementation.
• Strong debugging, problem-solving, and technical leadership skills.