Lead Engineer

Quest Global; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Quest Global is seeking a senior ASIC/SoC physical design engineer in Bengaluru to own the RTL-to-GDSII flow and drive physical implementation across advanced nodes. The role includes floor planning, CTS, and 3D‑IC signoff for multi‑die assemblies with TSV planning and STA.

You will collaborate with IP and foundry partners to build methodologies and automation scripts using Tcl, Python, or Perl to optimize performance and power.

Qualifications

• 5–10+ years of hands-on ASIC/SoC physical design experience with multiple full-cycle tap-outs at advanced nodes (5 nm, 3 nm, or 2 nm).
• Deep knowledge of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.
• Mandatory proficiency in Tcl; proficiency in Python or Perl desirable.

Responsibilities

• Own the RTL-to-GDSII flow, including physical‑aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
• Conduct 3D‑IC and signoff execution on 3D heterogeneous integration and multi‑die assemblies, managing TSV (Through‑Silicon Via) planning, IR drop, electro‑migration (EM), and static timing analysis (STA).
• Focus on low‑power implementation using UPF/CPF and achieve strict timing closure for high‑frequency designs (>1 GHz).
• Collaborate with IP and foundry partners to develop methodology and automation scripts in Tcl, Python, or Perl.

Skills

Physical design

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Synopsys ICC2

Synopsys PrimeTime

Tcl

Python

Perl

Job description

Key Responsibilities

• Own the RTL-to-GDSII flow, including physical‑aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).
• Conduct 3D‑IC and signoff execution on 3D heterogeneous integration and multi‑die assemblies, managing TSV (Through‑Silicon Via) planning, IR drop, electro‑migration (EM), and static timing analysis (STA).
• Focus on low‑power implementation using UPF/CPF and achieve strict timing closure for high‑frequency designs (>1 GHz).
• Collaborate with IP and foundry partners to develop methodology and automation scripts in Tcl, Python, or Perl.

Required Experience & Skills

• 5–10+ years of hands‑on ASIC/SoC physical design experience with multiple full‑cycle tap‑outs at advanced nodes (5 nm, 3 nm, or 2 nm).
• Deep knowledge of multi‑corner multi‑mode (MMCM), signal integrity, and 3D packaging technologies.
• Expertise with industry‑standard EDA tools such as Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).
• Mandatory proficiency in Tcl; proficiency in Python or Perl desirable.