DFT Technical Lead

Mirafra Technologies; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Mirafra Technologies seeks an experienced DFT Technical Lead/Manager to drive strategy, architecture, implementation, and validation of Design-for-Test methodologies for next-generation SoCs and ASICs.

You will define the overall DFT architecture, develop test strategies covering Scan, ATPG, MBIST, LBIST, and IJTAG (IEEE 1687), and lead DFT insertion and verification across blocks and full-chip levels. Strong hands-on expertise in Scan, ATPG, MBIST, LBIST, and silicon debug is required.

Qualifications

• Expert in DFT architecture for complex SoCs and ASICs.
• Experience with Scan, ATPG, MBIST, LBIST, IJTAG (IEEE 1687).
• Hands-on in DFT timing, pattern generation, and silicon debug.
• Ability to drive DFT strategy, validation, and integration with Physical Design.

Responsibilities

• Define and drive DFT architecture for multi-core/multi-die designs.
• Lead DFT insertion and verification at block and full-chip levels.
• Generate and optimize ATPG patterns and test strategies.
• Collaborate with Physical Design, STA, and ATE teams to achieve timing closure.

Skills

DFT

SoC/ASIC DFT

GLS

Tools

IJTAG 1687

ATPG

MBIST

LBIST

Job description

We are looking for an experienced DFT Technical Lead/Manager to drive the strategy, architecture, implementation, and validation of Design-for-Test methodologies for next-generation SoCs and ASICs.

DFT Architecture & Strategy

• Define and drive the overall DFT architecture for complex SoCs, multi-core, and multi-die designs.
• Develop test strategies covering Scan, ATPG, MBIST, LBIST, and IJTAG (IEEE 1687).
• Drive trade-offs across test coverage, area overhead, pin count, test time, and manufacturing cost.
• Establish DFT methodologies and flows aligned with product and manufacturing requirements.
• Lead DFT insertion and verification at both block and full-chip levels.
• Generate and optimize high-quality ATPG patterns, including Stuck-at, Transition Delay, Path Delay, and Cell-Aware testing.
• Drive pre-layout and post-layout Gate-Level Simulation (GLS) with timing annotations.
• Own DFT timing constraints and work closely with Physical Design and STA teams to achieve timing closure.
• Debug and resolve complex DFT implementation and verification issues.
• Strong experience in DFT/Design-for-Test for complex SoCs or ASICs.
• Hands-on expertise in Scan, ATPG, MBIST, LBIST, IJTAG/IEEE 1687, and DFT verification.
• Experience with full-chip DFT implementation and test architecture.
• Strong understanding of DFT timing, ATPG coverage, pattern generation, GLS, and silicon debug.
• Experience working with Physical Design, STA, Verification, and ATE teams.