Lead DFT Engineer / DFT Manager

foundit; Bengaluru Urban; On-site; INR 3,500,000 - 5,200,000; Full time

Job summary

foundit seeks a senior DFT professional to lead end-to-end DFT architecture, strategy, and sign-off for complex SoCs/IPs in Bengaluru. You will drive JTAG/iJTAG, BSCAN, ATPG, MBIST, and memory test strategies while coordinating with cross-functional teams.

You will mentor a team of DFT engineers, review plans and coverage, and push for automated methodologies and robust test quality across multiple projects.

Qualifications

• Senior DFT professional with hands-on expertise in end-to-end DFT for SoCs/IPs.
• Experience defining and owning DFT strategy and architecture.

Responsibilities

• Lead end-to-end DFT architecture, implementation, and signoff for SoC/IP programs.
• Define and own DFT strategy including scan architectures, JTAG/iJTAG, BSCAN, ATPG, MBIST.
• Review and approve DFT plans, test architectures, and coverage targets.
• Drive ATPG, MBIST, and DFT simulation flows and signoff quality.
• Lead silicon bring-up, debug, and yield improvement from a DFT perspective.
• Manage and mentor a team of DFT engineers; coordinate with Design, PD, Validation, Product.

Skills

JTAG/iJTAG

BSCAN

ATPG

MBIST

Memory test

DFT simulation

SoC test architecture

Education

B.Tech in Electronics

M.Tech in VLSI

Tools

Synopsys

Cadence

Siemens

Job description

We are looking for a senior DFT professional to lead DFT strategy, execution, and team delivery for complex SoCs/IPs. This role requires strong hands-on DFT expertise along with team leadership, technical ownership, and cross-functional coordination.

Key Responsibilities

• Lead end-to-end DFT architecture, implementation, and signoff for SoC/IP programs
• Define and own DFT strategy: Scan architectures, JTAG/iJTAG, BSCAN, ATPG, MBIST
• Review and approve DFT plans, test architectures, and coverage targets
• Drive ATPG, MBIST, and DFT simulation flows and signoff quality
• Lead silicon bring-up, debug, and yield improvement from a DFT perspective
• Manage and mentor a team of DFT engineers (task allocation, reviews, technical guidance)
• Conduct design and DFT reviews with stakeholders (Design, PD, Validation, Product)
• Drive schedule, risk management, and delivery commitments for DFT milestones
• Establish and improve DFT methodologies, best practices, and automation
• Interface with customers and management on DFT status, issues, and plans

Required Technical Skills

• Strong hands-on experience in:
• JTAG/iJTAG, BSCAN
• Scan architectures (full scan, compression, hierarchical DFT)
• ATPG (stuck-at, transition, at-speed)
• MBIST and memory test strategies
• DFT simulation and debug (RTL and gate-level)
• Solid understanding of SoC test architecture, test coverage, and test quality metrics
• Experience with industry DFT tools (Synopsys/Cadence/Siemens or equivalent)

Leadership/Management Requirements

• Proven experience as a Team Lead/Technical Lead/DFT Manager
• Experience in leading and mentoring engineers, technical reviews, and signoff ownership
• Planning and tracking deliverables across multiple projects
• Stakeholder management and cross-team coordination
• Ability to drive technical decisions and resolve complex DFT issues

Good To Have

• Experience with low-power DFT, IJTAG networks, and advanced test compression
• Experience handling multiple SoCs or large, complex chips
• Customer-facing or program leadership experience

Education

• B.Tech/M.Tech in Electronics, VLSI, or a related field