Senior/ Lead Design Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks an experienced Design Verification Lead with 5–15 years of hands-on expertise in SystemVerilog and UVM verification to drive end-to-end verification efforts for IP, Subsystem, and SoC designs.

You will develop verification plans, build robust testbenches, and lead coverage closure while mentoring team members and coordinating with RTL and architecture teams to ensure successful sign-off. Bengaluru on-site position.

Qualifications

• Experience in SystemVerilog and UVM verification.
• IP/Subsystem/SoC verification experience.
• Strong knowledge of functional and code coverage, assertions, and debugging.
• Familiarity with high-speed protocols such as DDR, Ethernet is a plus.

Responsibilities

• Develop and execute verification plans for IP, Subsystem, and SoC designs.
• Build and maintain SystemVerilog and UVM-based verification environments.
• Develop testbenches, sequences, test cases, and reusable verification components.
• Perform functional verification, assertion-based verification, and coverage closure.
• Debug complex simulation failures and collaborate with RTL, architecture, and design teams.
• Drive verification from planning through execution and final sign-off.

Skills

SystemVerilog and UVM

IP/SoC verification

Functional & code coverage

Debugging & root-cause analysis

Tools

Python

Perl

Shell scripting

Job description

Experience: 5–15 Years

Notice Period: 0–30 Days

Key Skills & Domain Expertise

We are looking for experienced Design Verification professionals with expertise in one or more of the following:

• High-Speed Protocols
• DDR
• Ethernet
• GLS (Gate-Level Simulation)
• RISC / RISC-V
• Develop and execute verification plans for IP, Subsystem, and SoC-level designs.
• Build and maintain robust SystemVerilog and UVM-based verification environments.
• Develop testbenches, sequences, test cases, and reusable verification components.
• Perform functional verification, assertion-based verification, and coverage closure.
• Debug complex simulation failures and collaborate with RTL, architecture, and design teams.
• Drive verification from planning through execution and final sign-off.

Required Skills

• Strong hands-on experience in SystemVerilog and UVM.
• Experience in IP, Subsystem, or SoC Verification.
• Expertise in one or more of the listed domains/protocols.
• Strong knowledge of functional coverage, code coverage, assertions, and debugging.
• Knowledge of Python, Perl, or Shell scripting is an added advantage.

Additional Requirements for Design Verification Lead

• Lead and drive end-to-end verification activities.
• Define verification strategies and plans.
• Drive coverage closure and resolve complex verification challenges.
• Mentor and guide team members.