Lead IP Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru seeks a Lead IP Verification Engineer to own verification strategy, testbench architecture, and signoff for complex digital IPs.

You will develop SystemVerilog/UVM testbenches, define VPlan, run regressions, and drive coverage closure while mentoring junior engineers and collaborating with RTL, architecture and SoC teams.

Qualifications

• 5–10 years of hands-on Design Verification experience, preferably with complex digital IPs.
• Strong expertise in SystemVerilog and UVM.
• Deep understanding of Testbench Architecture and verification methodologies.

Responsibilities

• Own IP verification strategy, planning, execution, and signoff for complex digital IPs.
• Architect and develop scalable SystemVerilog/UVM testbenches.
• Define and execute VPlan, test scenarios, regressions, and coverage closure.
• Develop and maintain UVM components including sequences, agents, monitors, scoreboards, and checkers.
• Perform comprehensive functional, corner-case, stress, and performance verification.
• Verify AMBA AXI, AHB, and APB protocols.
• Drive performance verification covering latency, throughput, bandwidth, backpressure, and stress scenarios.
• Lead simulation regressions, failure triage, debug and root-cause analysis.
• Leverage formal verification to identify functional gaps and improve verification quality.
• Collaborate closely with RTL, architecture, performance, and SoC teams.
• Drive verification milestones and ensure high-quality, on-time delivery.
• Mentor engineers and contribute to verification methodology and flow improvements.

Skills

SystemVerilog

UVM

IP-level verification

Testbench Architecture

AXI/AHB/APB protocols

Performance verification

Debugging

Mentoring

Verification signoff

Python/Perl/Tcl

Tools

Synopsys VCS

Cadence simulators

JasperGold

Synopsys VC Formal

Job description

We are looking for a Lead IP Verification Engineer with strong expertise in IP-level Design Verification and Testbench Architecture. The ideal candidate will take end-to-end ownership of verification strategy, testbench development, execution, debug, and signoff for complex digital IPs.

Key Responsibilities

• Own IP verification strategy, planning, execution, and signoff for complex digital IPs.
• Architect and develop scalable SystemVerilog/UVM testbenches.
• Define and execute VPlan, test scenarios, regressions, and coverage closure.
• Develop and maintain UVM components including sequences, agents, monitors, scoreboards, and checkers.
• Perform comprehensive functional, corner-case, stress, and performance verification.
• Verify AMBA AXI, AHB, and APB protocols.
• Drive performance verification covering latency, throughput, bandwidth, backpressure, and stress scenarios.
• Lead simulation regressions, failure triage, debug and root-cause analysis.
• Leverage formal verification to identify functional gaps and improve verification quality.
• Collaborate closely with RTL, architecture, performance, and SoC teams.
• Drive verification milestones and ensure high-quality, on-time delivery.
• Mentor engineers and contribute to verification methodology and flow improvements.

Required Technical Expertise

• 5–10 years of hands-on experience in Design Verification, preferably with complex digital IPs.
• Strong expertise in SystemVerilog and UVM.
• Deep understanding of Testbench Architecture and verification methodologies.
• Strong experience with IP-level verification, VPlan, regressions, and coverage closure.
• Hands-on experience with AXI / AHB / APB protocols.
• Strong performance verification experience.
• Hands-on experience with Synopsys VCS and/or Cadence simulators.
• Experience with JasperGold and/or Synopsys VC Formal.
• Strong debugging and root-cause analysis skills.
• Experience driving verification signoff and technical execution.
• Strong communication, ownership, leadership, and mentoring capabilities.

Good to Have

• Experience with complex SoC subsystems or high-performance IPs.
• Strong knowledge of SVA, functional coverage, constrained-random verification, and assertions.
• Experience integrating simulation and formal verification methodologies.
• Proficiency in Python, Perl, or Tcl for verification automation.