Digital Verification Lead Engineer

Mulya Consulting; Hyderabad; On-site; INR 1,500,000 - 2,400,000; Full time

Job summary

Mulya Consulting in Hyderabad seeks a Senior Design Verification Engineer with 10+ years in semiconductor verification, especially FPGA or ASIC. You will verify complex designs, develop constrained random test benches, and ensure trade-offs between quality and schedule.

Familiarity with SerDes and PCIe/USB/DP is a plus, and you will participate in design reviews with cross-functional teams. You will plan verification activities, implement debug flows, and maintain the verification environment,

Qualifications

• 10+ years experience in the semiconductor industry.
• Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC
• Skilled in trade-offs between quality and schedule
• Experience in constrained random test bench development
• Familiarity with SerDes and high-level protocols (e.g., PCIe, USB, DP) would be advantageous
• Extensive digital verification background with some UVM experience

Responsibilities

• Develop design verification methodologies and implement standard debug flows
• Work with designers in verification and validation of circuit designs
• Participate in design reviews
• Prepare design verification plan based on design specifications
• Plan and schedule assigned projects for timely completion
• Utilize the latest techniques, tools, and technologies for design verification activities
• Maintain design verification environment and track & close design bugs

Skills

Semiconductor industry experience

FPGA/ASIC verification

UVM experience

Trade-off management

High-level protocols knowledge

Tools

SystemVerilog

Simulation tools

Job description

Role & responsibilities

• Develop design verification methodologies and implement standard debug flows
• Work with designers in verification and validation of circuit designs
• Participate in design reviews
• Prepare design verification plan based on design specifications
• Plan and schedule assigned projects for timely completion
• Utilize the latest techniques, tools, and technologies for design verification activities
• Maintain design verification environment and track & close design bugs

Preferred candidate profile

• 10+ years experience in the semiconductor industry
• Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC
• Skilled in trade-offs between quality and schedule
• Experience in constrained random test bench development
• Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
• Extensive digital verification background with some UVM experience