lead Design Engineer

Cadence Design Systems, Inc.; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Cadence Design Systems, Inc. in India seeks an ASIC verification engineer to verify IP, sub-systems and SOCs, develop test plans and functional coverage, and implement coverage bins. You will participate in post-silicon validation and bring-up efforts, contributing to impactful semiconductor projects.

The role requires strong Verilog, HVL (SV/Specman), UVM/OVM/eRM experience, plus scripting and collaboration skills across teams.

Qualifications

• BS/MS in ECE or CS with 4+ years of related experience.
• Strong debugging and cross-team communication skills.

Responsibilities

• Work at IP, sub-system and SOC level verification.
• Create test plans and functional coverage plans; code functional coverage bins.
• Involved in post-silicon validation and bring-up.

Skills

Verilog

SV/Specman

UVM/OVM/eRM

Functional coverage

Test plan

PCIe verification

LPDDR verification

Scripting

Team collaboration

Education

BS/MS in ECE or CS

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design verification of ASICs for Palladium.

Position is based in Bangalore. Will have to work at IP, Sub-System and SOC level verification. Test plan creation, functional coverage plan and coding of functional coverage bins. Will be involved in post silicon validation/bring up.

Job Requirements

• Strong expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology.
• Experience in functional coverage/code coverage/assertions development and closure.
• Experience in test plan creation.
• Exposure to PCIe and LPDDR verification.
• Strong debug skills Should be process oriented and have a passion for scripting/automation.
• Should be a good team player Effective cross-team communication and documentation skill is strongly preferred.
• Minimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in related fields.

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Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. We welcome your interest in the company and want to make sure our job site is accessible to all.

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.