Lead Verification Engineer

Cadence Design Systems; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cadence Design Systems is seeking a Product validation engineer with strong HDL knowledge to work on Palladium technologies. Based in Noida/Bangalore, the role involves verifying upcoming features, managing regressions, and ensuring high-quality releases while mentoring juniors.

The candidate should have experience with SystemVerilog, C++, UVM, and EDA tools, with a background in Emulation/UPF being a strong plus.

Qualifications

• Electrical/ Electronics or CS Engineer with good HDL understanding.
• Experience in Emulation/UPF is a big plus.
• Familiarity with SystemVerilog, C++, UVM and HVL for functional verification.

Responsibilities

• Verify Palladium features and upcoming capabilities; manage regressions.
• Review technical deliverables and guide juniors on design/verification tasks.
• Ensure quality of releases for Palladium emulation technology; mentor team members.

Skills

HDL Verilog/VHDL

SystemVerilog

C++

UVM

Scripting

Emulation/UPF

Education

B.Tech/BE/ME/MTech

Tools

Palladium

EDA tools

Job description

About Cadence

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary

We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in Emulation domain. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.

Position Description

Product validation engineer to work on key Palladium technologies including UPF. Position is based in Noida/Bangalore. Role involves verification of various upcoming features in Palladium. Work also involves managing current set of regressions. Participate in technical discussions, including Functional Specification reviews, Testplan reviews etc. Review and guide team members on technical deliverables from the team. Person will be fully responsible and accountable for quality of releases and features for Palladium emulation technology. Mentor juniors in the team. Contribute towards the improvement of existing emulation validation/verification flows.

Position Requirements

The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in Emulation/UPF will be big plus. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) specially Palladium with focus towards debugging design/ verification problems. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. B. Tech/BE/ M. Tech / ME with 3+ years of relevant experience.

Behavioral Skills Required

Must possess strong written, verbal and presentation skills. Good communication and interpersonal skills, demonstrate teamwork and collaboration skills. Ability to establish a close working relationship with both customer peers and management. Explore what’s possible to get the job done, including creative use of unconventional solutions. Work effectively across functions and geographies. Push to raise the bar while always operating with integrity.

Equal Employment Opportunity Policy

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.