Lead Design Engineer ( Synthesis/LEC/CLP )

Cadence Design Systems; Ahmedabad District; On-site; INR 2,600,000 - 3,800,000; Full time

Job summary

Cadence Design Systems is seeking a Lead Design Engineer to provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. The role emphasizes debugging synthesis/LEC issues and contributing to CLP sign-off while coordinating with PD, DFT, and RTL teams.

The candidate will write constraints, ECO scripts and work on complex escalations, with a strong emphasis on ownership and cross-functional collaboration.

Qualifications

• 5–8 years hands-on experience in ASIC synthesis, LEC, or low-power verification.
• Deep knowledge of Genus and Conformal for LEC/CLP.
• Experience with UPF-based power intent (IEEE 1801).

Responsibilities

• Run and debug LEC sign-off on design blocks and fix NEQs and constraint mismatches.
• Run Genus synthesis to improve QoR and debug SDC/constraint issues.
• Support CLP flows and write timing/power constraints.
• Write and maintain ECO scripts for design blocks.
• Triage and document issues; escalate systemic problems.
• Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues.
• Prepare clear status updates and technical summaries.

Skills

ASIC synthesis

Genus/Conformal

UPF power intent

Scripting: Tcl/Perl/Python

Unix/Linux environment

Digital design fundamentals

Low-power verification

Communication skills

Education

BE/BTech/ME/MS/MTech in Electrical/Electronic

Tools

Cadence Genus

Cadence Conformal

Linux/Unix

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Experience: 5-8 Years BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

Location: Bangalore/Ahmedabad/Pune

About the Role

We are looking for a Lead Design Engineer to provide hands-on execution across Synthesis, LEC, CLP, and UPF/power-intent flows for advanced ASIC/SoC designs. This role is execution-focused with growing ownership: debugging synthesis and LEC issues independently, contributing to CLP sign-off, and writing constraints and ECO scripts, while working closely with the Team on complex escalations.

Key Responsibilities

• Run and debug LEC sign off on design blocks; investigate and resolve NEQs and constraint mismatches
• Work on Genus synthesis runs to improve QoR, debug SDC/constraint issues
• Support CLP flows
• Write and maintain ECO scripts and timing/power constraints for design blocks
• Independently triage and document issues, escalating complex or systemic issues as needed
• Collaborate with PD, DFT, and RTL teams to resolve cross-functional issues affecting synthesis/LEC/CLP closure
• Prepare clear status updates and technical summaries for internal tracking

Required Skills

• 5-8 years of hands-on experience in ASIC synthesis, LEC, and/or low-power verification flows
• Working knowledge of Cadence Genus and Conformal (LEC and/or CLP)
• Familiarity with UPF/CPF-based power intent (IEEE 1801)
• Scripting proficiency in Tcl, Perl, or Python; comfortable in Unix/Linux based environments
• Solid understanding of digital design fundamentals, STA basics, and low-power architecture concepts
• Strong communication skills and ability to work independently on assigned blocks

Equal Employment Opportunity Policy

Cadence is committed to equal employment opportunity throughout all levels of the organization. We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [e-mail].

Cadence participates in the E-Verify program in certain U.S. locations as required by law.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.