Sr Principal Software Engineer

Cadence Design Systems; Bengaluru; On-site; INR 3,500,000 - 5,000,000; Full time

Job summary

Cadence Design Systems in Bangalore/Noida seeks a Sr. Principal Software Engineer to drive advanced RTL-based solutions for timing, area and power. You will mentor peers and contribute to cutting-edge EDA tools in a research-driven environment.

You’ll work on debugging, feature development and optimization of synthesis results, using Verilog/VHDL, Xcelium and DFT/MBIST concepts, with a strong focus on reliability and performance.

Qualifications

• Hands-on experience in RTL Coding.
• Write, update, and optimize RTL code using VHDL or Verilog.
• Run functional simulations, static timing analysis, and design-for-test checks.
• Knowledge of DFT/MBIST is a plus.

Responsibilities

• R&D support of application and product engineers for customer problems and requests.
• Problem analysis, debugging and fixing, or developing new features to improve synthesis results.
• Mentoring and support to develop programming skills within Cadence.

Skills

RTL Coding

Verilog

VHDL

Functional Simulations

Static Timing Analysis

DFT

MBIST

Education

BE/BTech/ME/MTech- Computer Science or others

Tools

Xcelium

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Sr. Principal Software Engineer Grade: T5 Experience: 12- 16 Years Location: Bangalore/Noida

Job Responsibilities:

R&D support of application and product engineers for customer problems and requests. This consists of problem analysis, debugging and fixing, or the development of new features and enhancements to improve synthesis results with respect to timing, area and power. This job will suit applicants looking to continue their software engineering career in an intellectually stimulating and challenging problem domain. There is a significant research element to the work that Cadence does that is truly innovative; we don’t know what the answers are when we start out! Mentoring and support will be provided to the successful candidate to both enable contribution to the large EDA problem domain and to develop their programming skills into professional software engineering skills.

Job Qualifications:

BE/BTech/ME/MTech- Computer Science or others

Required Skills

The candidate should have hands‑on experience in RTL Coding. The candidate should be able to write, update, and optimize register‑transfer level code using System Design Guide standards in VHDL or Verilog. run functional simulations (using Xcelium), static timing analysis, and design‑for‑test checks to find bugs. validate, test, and investigate performance/accuracy issues in the simulator. Knowledge of Design-For-Test (DFT) and/or Memory-Built‑In‑Self‑Test (MBIST) is a plus.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.