Principal Design Engineer

Cadence Design Systems; Dadri; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Cadence is seeking a seasoned verification engineer for the Xtensa Functional Safety Design Verification Team in India. You will develop and verify hardware and software safety mechanisms, build test benches, and create diagnostics in assembly/C.

You will drive assertion checks, coverage monitoring, and fault simulations to support safety certification. Collaboration with RTL, EDA, and Safety teams is essential to success.

Qualifications

• BS or higher in EE/Computer Engineering.
• 8–10 years design verification experience.
• Experience leading a small team.
• Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals.
• Expertise with Verilog and SystemVerilog assertions and functional coverage.
• Good working knowledge of scripting languages like Perl, Unix shell or similar languages.
• Knowledge of ISO 26262 and safety concepts and requirement specifications.
• Proficient with C language and assembly language.
• Excellent written and oral communication skills necessary.
• Exposure to debugging netlist/gate level simulation.
• General understanding OS.
• Exposure to MISRA coding guidelines.
• Experience in fault simulation tools and methodologies.

Responsibilities

• Develop and verify hardware and software safety mechanisms for Xtensa processors.
• Implement simulation or emulation test benches and assembly/C language diagnostics.
• Create assertion checkers or coverage monitors to meet target safety goals.
• Assist with fault simulation and analyze coverage information.
• Collaborate with RTL, EDA, and Functional Safety teams.
• Produce functional safety work products and documentation for safety certification.

Skills

Verilog

SystemVerilog

Functional safety

C language

Assembly

Scripting

MISRA

Debugging

Communication

Architecture

Education

Bachelor in EE/CE

Tools

EDA simulators

Perl

Unix shell

MISRA tooling

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing presence in the Automotive Safety market.

As a member of the Functional Safety Design Verification Team for Xtensa processors you will be responsible for development and verification of hardware and software safety mechanisms. You will implement simulation or emulation test benches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target safety and product verification goals. You will also assist with fault simulation and analyzing coverage information. You will work closely with the RTL, EDA, and Functional Safety teams. You will develop and deliver functional safety work products, including documentation needed for product safety certification.

Required Skills and Experience:

• 8-10 years of design verification experience
• BS (or higher) in EE/Computer Engineering
• Experience in leading a small team
• Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
• Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
• Good working knowledge of scripting languages like Perl, Unix shell or similar languages
• Knowledge of technical safety concepts and requirement specifications according to ISO 26262
• Proficient with C language and assembly language
• Excellent written and oral communication skills necessary
• Exposure to debugging netlist/gate level simulation
• General understanding OS
• Exposure to MISRA coding guidelines
• Experience in fault simulation tools and methodologies

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