Lead ASIC PD / EMIR Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; Sur place; INR 400 000 - 700 000; Plein temps

Résumé du poste

SmartSoC Solutions Pvt Ltd is seeking a Lead ASIC PD / EMIR Engineer to own IR drop, EMIR and PDN sign-off for advanced digital SoCs. You will drive EMIR closure, debug complex issues, and work closely with the PD team to ensure robust power integrity across the chip.

The role requires extensive VLSI/Physical Design experience, hands-on EMIR closure, and strong cross-functional collaboration to meet performance and reliability targets.

Qualifications

• 8+ years of overall VLSI/Physical Design experience.
• 3+ years of hands-on PDN and EMIR closure for digital ASIC designs.
• Strong expertise with industry-standard EMIR analysis and sign-off methodologies.
• Excellent debugging, analytical, and cross-functional collaboration skills.

Responsabilités

• Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
• Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
• Collaborate with the Physical Design team to drive efficient IR/EM closure across the chip.
• Analyze PDN and recommend improvements for robust power integrity.
• Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.

Connaissances

PDN

EMIR

IR drop

Power integrity

Sign-off

Cross-functional

Description du poste

We're Hiring | Lead ASIC PD / EMIR Engineer

Are you passionate about power integrity and sign-off for advanced digital SoCs? We're looking for an experienced PDN / EMIR Engineer to join our growing VLSI team.

Required Experience

• 8+ years of overall VLSI/Physical Design experience is preferred.
• 3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
• Strong expertise with industry-standard EMIR analysis and sign-off methodologies.
• Excellent debugging, analytical, and cross-functional collaboration skills.

Key Responsibilities

• Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
• Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
• Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
• Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
• Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.