IO Layout Engineer

Exiger Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Exiger Technologies in Bengaluru seeks an experienced IO Layout Engineer to design and optimize IO layouts for advanced nodes, including ESD structures and analog IOs. You will perform floor planning, placement, routing, and parasitic extraction, and drive sign-off with circuit and verification teams.

The role requires 3–8 years of IO layout experience, proficiency with Cadence Virtuoso and Calibre/Assura, and scripting ability (Python/Tcl/Perl). Knowledge of 28nm and below nodes is a plus.

Qualifications

• 3–8 years of IO or custom layout experience.
• Proficient with Cadence Virtuoso and Calibre/Assura for layout verification.
• Experience with 28nm and below nodes; strong IO design concepts.
• Scripting knowledge in Skill, Tcl, Perl, or Python preferred.

Responsibilities

• Create and optimize IO circuit layouts including ESD structures and analog IOs.
• Perform floor planning, placement, routing, and parasitic extraction.
• Ensure DRC, LVS, ERC compliance using industry-standard tools.
• Collaborate with circuit and verification teams for sign-off.
• Automate layout flows using scripting for productivity.

Skills

IO Layout

Cadence Virtuoso

Calibre/Assura

Advanced Node Design

Python scripting

Tools

Cadence Virtuoso

Calibre/Assura

Job description

We are looking for an experienced IO Layout Engineer to join our team in Bangalore. The role involves custom IO layout design, optimization, and sign-off at advanced technology nodes.

Responsibilities:

• Create and optimize IO circuit layouts including ESD structures and analog IOs.
• Perform floor planning, placement, routing, and parasitic extraction.
• Ensure DRC, LVS, ERC compliance using industry-standard tools.
• Collaborate with circuit and verification teams for sign-off.
• Automate layout flows using scripting for better productivity.

Required Skills:

• 3-8 years in IO / Custom Layout.
• Strong knowledge of Cadence Virtuoso and Calibre/Assura verification.
• Experience with advanced nodes (28nm & below).
• Good understanding of device physics & IO design concepts.
• Scripting knowledge (Skill/Tcl/Perl/Python) preferred.