Analog Layout Engineer

Endivite Technologies; Bengaluru; Hybrid; INR 1,500,000 - 2,100,000; Full time

Job summary

Endivite Technologies in Bengaluru, India, is seeking experienced Analog Layout Engineers with hands‑on experience in custom analog layout design, physical verification, and advanced semiconductor technology nodes.

You will design and optimize analog and mixed‑signal layouts, perform floor planning, routing, DRC/LVS checks, and collaborate with circuit teams to tape‑out devices.

Qualifications

• 5+ years of hands-on experience in Analog Layout Design.
• Strong knowledge of MOS device layout, matching techniques, guard rings, shielding, and parasitic reduction.
• Experience with Cadence Virtuoso Layout Editor and physical verification tools such as Calibre or equivalent.

Responsibilities

• Design and develop custom analog and mixed-signal layouts based on circuit schematics.
• Perform floor planning, device placement, routing, and layout optimization.
• Work on matching-critical circuits, including differential pairs, current mirrors, and other analog building blocks.
• Perform DRC, LVS, and other physical verification checks to ensure layout quality.
• Resolve physical verification errors and optimize layouts for area, performance, and manufacturability.
• Collaborate with circuit design, integration, and verification teams.
• Support layout reviews, block integration, and tape-out activities.

Skills

Analog Layout Design

MOS device layout

Matching techniques

Cadence Virtuoso

Calibre LVS/DRC

Layout optimization

Education

Bachelor's or Master's in ECE/EEE

Tools

Cadence Virtuoso Layout Editor

Calibre

Job description

Job Description

Endivite Technologies is looking for experienced Analog Layout Engineers with strong hands‑on experience in custom analog layout design, physical verification, and advanced semiconductor technology nodes.

Key Responsibilities

• Design and develop custom analog and mixed-signal layouts based on circuit schematics.
• Perform floor planning, device placement, routing, and layout optimization.
• Work on matching-critical circuits, including differential pairs, current mirrors, and other analog building blocks.
• Perform DRC, LVS, and other physical verification checks to ensure layout quality.
• Resolve physical verification errors and optimize layouts for area, performance, and manufacturability.
• Collaborate with circuit design, integration, and verification teams.
• Support layout reviews, block integration, and tape-out activities.

Required Skills

• 5+ years of hands‑on experience in Analog Layout Design.
• Strong knowledge of MOS device layout, matching techniques, guard rings, shielding, and parasitic reduction.
• Experience with Cadence Virtuoso Layout Editor and physical verification tools such as Calibre or equivalent.
• Good understanding of DRC, LVS, and layout‑dependent design rules.
• Experience with custom analog and mixed‑signal IP layout.
• Exposure to advanced technology nodes is an advantage.

Preferred Qualifications

• Bachelor's or Master's degree in ECE, EEE, or a related discipline.
• Experience in technology nodes such as 180nm, 65nm, 28nm, 16nm, or below is preferred.