Hiring ASIC/RTL Design Engineer | HYD | Mirafra Technologies

Mirafra; Hyderabad; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Mirafra in Hyderabad is seeking an ASIC/RTL Design Engineer with 5+ years of experience to work on RTL design using Verilog/VHDL. You will develop FPGA Vivado flows from synthesis to bitstream, ensure timing and IO constraints, and implement system-level concepts including AXI/AMBA.

Strong debugging skills with ILA and Linux proficiency are required. Join a cross-functional team and contribute to design verification and automation of flows using Perl/Tcl/Python.

Qualifications

• 5+ years of RTL digital design experience.
• Strong in Verilog/VHDL.
• Experience with FPGA Vivado and bitstream generation.
• Knowledge of timing constraints, IO LOC, and placement.
• System-level architecture knowledge including AXI/AMBA protocols.
• Excellent waveform debugging using ILA and similar tools.
• Ability to collaborate with cross-functional teams.
• Proficiency in Unix environment.
• Scripting in Perl/Tcl/Python for flow automation.

Responsibilities

• Design RTL in Verilog/VHDL for ASIC/FPGA projects.
• Develop FPGA Vivado flows from synthesis through implementation to bitstream generation.
• Analyze and optimize timing constraints and IO locations.
• Incorporate system-level concepts using AXI/AMBA and related buses.
• Debug waveforms and validate designs using ILA and related tools.
• Collaborate with cross-functional teams to deliver IP blocks and integration.
• Automate verification and flows using scripting in Perl/Tcl/Python.

Skills

RTL design

Verilog/VHDL

FPGA Vivado

Timing constraints

IO LOC & placement

AXI/AMBA

Video IPs

Ethernet/USB

Waveform debugging

Unix scripting

Automation flows

Version control

Tools

Vivado

Ila/Debug tools

Perforce/Github

Job description

ASIC/RTL Design Engineer

Exp - 5 + yrs

Location - Hyderabad

Availability - Candidate must join within 0 to 30 days

• Strong in RTL digital design with Verilog/VHDL.


• Strong familiarity with FPGA Vivado Design creation, taking it through Synthesis, implementation, bit-stream generation.


• Thorough understanding of the design constraints ( timing , IO LOC, placement etc.,)


• Knowledge of system-level architecture including buses like AXI/AHB/CHI/ACE5, bridges, video IPs like ISP/Encoder/Decoder and peripherals such as USB and Ethernet


• Excellent waveform debug skills using front end industry standard design tools like ILA, verification waveforms.


• Demonstrate the ability to work with cross-functional teams


• Proficiency in Unix environment


• Good knowledge in scripting(Perl/Tcl/Python) and automation of verification flows/process


• Familiarity with presi platforms would be usefulRTL designer is expected to have strong expertise on AMD/Xilinx Vivado tools, IP understanding, System level design understanding, IP product guide understanding, Version management tools(Perforce,Github) , AMBA protocols(AXI4,AXIS) and strong Linux skills.