Hiring 3+ Verification Engineers -Mirafra Technologies HYD

Mirafra; Hyderabad; On-site; INR 1,100,000 - 1,900,000; Full time

Job summary

Mirafra Technologies in Hyderabad is seeking a Design Verification Engineer with 3–5 years of hands-on experience in SystemVerilog and UVM to build and maintain verification environments for IP and subsystems. You will develop test plans, execute constrained-random tests, and drive coverage closure.

The role involves collaborating with Architecture, RTL Design, and Validation teams, supporting SoC verification, and preparing detailed verification reports and status updates.

Qualifications

• 3–5 years of Digital Design Verification experience.
• Proficient in SystemVerilog and UVM.
• Experience in constrained-random verification and coverage-driven verification.
• Strong debugging and root-cause analysis skills.
• Understanding of RTL design and testbench development.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for IP and subsystem verification.
• Create and execute verification test plans aligned with design specifications.
• Perform constrained-random and directed testing.
• Implement and drive functional and code coverage closure.
• Debug RTL and testbench failures using waveform analysis and standard tools.
• Collaborate with Architecture, RTL Design, and Validation teams.
• Support SoC-level verification and IP integration when required.
• Manage regressions, failure triage, and testbench optimization.
• Prepare verification reports, documentation, and status updates.

Skills

SystemVerilog

UVM

UVM Testbench Development

Constrained-Random Verification

Coverage-Driven Verification

Digital Logic Design

State Machines

Synchronous Design Principles

Debugging

Verification Sign-off

Education

Bachelor’s or Master’s degree in Electrical Engineering

Bachelor’s or Master’s degree in Electronics

Bachelor’s or Master’s degree in Computer Engineering

Job description

Mirafra Technologies is Hiring Design Verification Engineer

Experience: 3–5 Years
Role: Design Verification (DV) Engineer

Availability - 0 to 30 days

Key Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for IP and subsystem-level verification.
• Create and execute verification test plans aligned with design specifications.
• Perform constrained-random and directed testing.
• Implement and drive functional and code coverage closure.
• Debug complex RTL and testbench failures using waveform analysis and industry-standard tools.
• Collaborate with Architecture, RTL Design, and Validation teams.
• Support SoC-level verification and IP integration when required.
• Manage regressions, failure triage, and testbench optimization.
• Prepare verification reports, documentation, and status updates.

Required Skills

• 3–5 years of experience in Digital Design Verification
• Strong hands-on experience in:
• SystemVerilog
• UVM
• UVM Testbench Development
• Constrained-Random Verification
• Coverage-Driven Verification
• Strong understanding of:
• Digital Logic Design
• State Machines
• Synchronous Design Principles
• Excellent debugging and root-cause analysis skills.
• Experience with functional/code coverage closure and verification sign-off.

Qualification

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.

Location: Hyderabad