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Qualcomm India Private Limited is seeking an experienced ASIC RTL Design Engineer in Bengaluru. The role demands 4–8 years of hands-on RTL design, Verilog/SystemVerilog proficiency, and a strong grasp of multi-clock domain blocks and AMBA protocols.
You will collaborate with verification teams to debug pre/post silicon issues and contribute to timing closure and low-power design. Ideal candidates hold a B.E./B.Tech or higher in CS/EE or related fields, with additional Master’s or PhD credentials