SoC RTL Design- Staff Engineer

Qualcomm; Chennai District; On-site; INR 800,000 - 1,200,000; Full time

Job summary

A leading technology company in Chennai seeks a Hardware Engineer specializing in ASIC and RTL design. The role requires 2+ years of experience with a focus on Logic design, SoC integration, and expertise in Verilog/System-Verilog. You will collaborate with verification teams and take part in pre/post Silicon debug processes. The ideal candidate holds a Bachelor's or higher in a relevant field and has strong hands-on experience with digital designs and ASIC tools.

Qualifications

• Experience in Logic design / micro-architecture / RTL coding.
• Hands on experience with SoC design and integration.
• Experience in Verilog/System-Verilog.
• Knowledge of AMBA protocols and SoC architectures.

Responsibilities

• Work with SoC verification and validation teams.
• Engage in pre/post Silicon debug.
• Develop constraints and timing closure.

Skills

Logic design

Micro-architecture

RTL coding

SoC design

Verilog/System-Verilog

AMBA protocols

Low power SoC design

Multi Clock designs

Education

Bachelor's degree in relevant field

Master's degree in relevant field

PhD in relevant field

Tools

Lint

CDC

Design compiler

Primetime

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Hardware Engineering

General Summary:

• Experience in Logic design / micro-architecture / RTL coding is a must.
• Must have hands on experience with SoC design and integration for SoCs.
• Experience in Verilog/System-Verilog is a must.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIe and SDCC.
• Understanding of Memory controller designs and microprocessors is an added advantage.
• Hands on experience in constraint development and timing closure.
• Work closely with the SoC verification and validation teams for pre/post Silicon debug.
• Hands on experience in Low power SoC design is required.
• Experience in Synthesis / Understanding of timing concepts for ASIC is required.
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Experience creating pad ring and working with the chip level floorplan team is an added advantage.
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Preferred Skills & Experience:

• 10-15 years of experience in digital front-end ASIC/RTL design.

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