SOC Design - Sr Lead

Qualcomm; Bengaluru; Sur place; INR 3 000 000 - 5 400 000; Plein temps

Résumé du poste

Qualcomm India Private Limited in Bengaluru requires an experienced hardware engineer with 8 to 11 years in ASIC/SoC design. You will handle logic design, RTL coding, and SoC integration for complex devices, using Verilog/SystemVerilog and AMBA protocols.

Collaboration with verification and validation teams is essential for pre/post silicon debug. Strong knowledge of low-power design, multi-clock designs, and timing closure is expected.

Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsabilités

• Work closely with the SoC verification and validation teams for pre/post Silicon debug.
• Collaborate on multi-clock designs and asynchronous interfaces.
• Contribute to low-power SoC design initiatives.

Connaissances

ASIC Design

SoC Design

Logic Design

RTL Coding

Verilog

AMS Protocols

Low Power Design

Multi Clock Design

Timing Closure

Floorplanning

Formation

Bachelor's in Electrical/Electronics Engineering

Master's in Electrical/Electronics Engineering

PhD in Electrical/Electronics Engineering

Outils

Design Compiler

Primetime

Lint

CDC

Synthesis

Description du poste

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

• 8 to 11 years of work experience in ASIC/SoC Design
• Experience in Logic design /micro-architecture / RTL coding is a must.
• Must have hands on experience with SoC design and integration for complex SoCs.
• Experience in Verilog/System-Verilog is a must.
• knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
• Understanding of Memory controller designs and microprocessors is an added advantage
• Work closely with the SoC verification and validation teams for pre/post Silicon debug
• Hands on experience in Low power SoC design is required
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
• Understanding of constraint development and timing closure is a plus.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience creating padring and working with the chip level floorplan team is an added advantage.
• Excellent oral and written communications skills
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.

Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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