GPU (RTL) Design - Sr Lead

Qualcomm; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru seeks an experienced hardware engineer to design and integrate ASIC RTL. You will work with verification and validation teams to debug pre/post silicon, leveraging Verilog/SystemVerilog and AMBA protocols.

The role emphasizes multi-clock domain blocks, low power design, and timing-conscious synthesis for robust ASIC flows. Candidates should have a Bachelor’s/Master’s/PhD in a related field with 3+ / 2+ / 1+ years of hardware experience respectively.

Qualifications

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 3+ years hardware engineering experience.
• Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years hardware engineering experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 1+ year hardware engineering experience.

Responsibilities

• Collaborate with verification and validation teams for pre/post silicon debugging.
• Design and integrate complex multi clock domain blocks.
• Apply knowledge of Verilog/SystemVerilog and AMBA protocols in hardware designs.
• Ensure timing closure and proper synthesis for ASIC flows.
• Support memory controller designs and microprocessor integration.

Skills

ASIC RTL Design

Logic design

RTL coding

Verilog/SystemVerilog

AMBA AXI/AHB/APB

Multi clock domain design

Low power design

Timing analysis

Synthesis/Timing concepts

Pre/Post Silicon debugging

Education

Bachelor's in CS/EE/Engineering or related

Master's in CS/EE/Engineering or related

PhD in CS/EE/Engineering or related

Tools

Lint

CDC

Design Compiler

PrimeTime

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

• Minimum 4 to 8 years of work experience in ASIC RTL Design
• Experience in Logic design/micro-architecture/RTL coding is a must.
• Must have hands on experience with design and integration of complex multi clock domainblocks
• Experience in Verilog/System-Verilog is a must.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
• Understanding of Memory controller designs and microprocessors is an added advantage
• Work closely with the Design verification and validation teams for pre/post Silicon debug
• Hands on experience in Low power design is preferable
• Experience in Synthesis / Understanding of timing concepts for ASIC is must

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  OR
  Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  OR
  PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

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