SoC RTL Design- Sr Staff Engineer

Qualcomm; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Qualcomm India Private Limited is seeking a hardware engineer skilled in logic design, RTL, and SoC integration for its Bengaluru team. You will work on Verilog/SystemVerilog and AMBA protocols, contributing to timing closure and low power design across ASIC flows.

You will collaborate with verification teams during pre/post silicon debug, assist with constraints and timing, and engage with floorplanning and pad ring activities to deliver robust SoCs.

Qualifications

• Bachelor’s degree with 2+ years hardware engineering experience or
• Master’s degree with 1+ year hardware experience or
• PhD in related field qualifies.

Responsibilities

• Collaborate with SoC verification and validation teams for pre/post silicon debug.
• Contribute to constraint development and timing closure.
• Assist in low power SoC design.
• Work with chip floorplan and pad ring teams.
• Use ASIC tools like Lint, CDC, Design Compiler, and PrimeTime.

Skills

Logic design

RTL coding

Verilog/SystemVerilog

AMBA protocols

SoC integration

Timing closure

Low power design

Synthesis

Primetime

Design Compiler

Lint

CDC

Education

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field

Tools

L integ

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

• Experience in Logic design /micro-architecture / RTL coding is a must.


• Must have hands on experience with SoC design and integration for SoCs.


• Experience in Verilog/System-Verilog is a must.


• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.


• Understanding of Memory controller designs and microprocessors is an added advantage


• Hands on experience in constraint development and timing closure


• Work closely with the SoC verification and validation teams for pre/post Silicon debug


• Hands on experience in Low power SoC design is required


• Experience in Synthesis / Understanding of timing concepts for ASIC is required.


• Hands on experience in Multi Clock designs, Asynchronous interface is a must.


• Experience creating pad ring and working with the chip level floorplan team is an added advantage


• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.


• OR


• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.


• OR


• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Preferred Skills & Experience:

• 12+ years of experience in digital front-end ASIC/RTL design.

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