Design Verification Engineer

ACL Digital; Chennai District; On-site; INR 1,000,000 - 1,800,000; Full time

Job summary

A leading semiconductor partner is hiring for a Mid-Senior level position focused on VLSI and Semiconductors in Chennai, India. Responsibilities include developing verification plans for complex SoC designs, performing RTL verification, and collaborating with teams to ensure accuracy. Applicants should have 5 to 10 years of relevant experience and expertise in bus protocols and SystemVerilog. This role offers full-time employment and the opportunity to be part of a dynamic engineering team.

Qualifications

• 5 to 10 years of experience in VLSI/semiconductor design and verification.
• Deep understanding of bus protocols and hands-on experience with AXI, AHB, APB.
• Experience in CPU (ARM/RISCV) subsystem verification and performance modeling.

Responsibilities

• Develop and execute verification plans for SoC designs and IP blocks.
• Architect testbenches using SystemVerilog and UVM/OVM.
• Perform RTL verification, simulation, and debugging.

Skills

Digital design and verification

Bus protocols understanding (AXI, AHB, APB)

CPU subsystem verification (ARM/RISCV)

SystemVerilog proficiency

UVM/OVM methodologies

Scripting languages (Perl, Tcl, Python)

Power-aware verification methodologies

Performance verification techniques

Analytical and debugging skills

Job description

Hiring Expertise/ Leaders for VLSI/ Semiconductors!

Experience: 5 to 10 Years

Job Description

• Develop and execute verification plans for complex SoC designs and IP blocks.
• Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies.
• Perform RTL verification, simulation, and debugging.
• Collaborate with design, architecture, and software teams to ensure functional correctness.
• Contribute to IP design reviews and sign-off processes.
• Support post-silicon validation and bring‑up activities.
• Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance.
• Conduct CPU subsystem verification (ARM/RISCV) including coherency, cache behavior, and interrupt handling.
• Perform power‑aware verification using UPF/CPF and validate low‑power design intent.
• Execute performance verification to ensure bandwidth, latency, and throughput targets are met.
• Perform gate‑level and timing simulations to sign off on timing closure.
• Analyze and verify serial peripherals like UART/SDIO/SPI and validate datapath integrity.

Preferred Skills & Experience

• 7–10 years of experience in digital design and verification.
• Deep understanding of bus protocols and bridge logic, including hands‑on experience with AXI, AHB, and APB.
• Experience with CPU (ARM/RISCV) subsystem verification and performance modeling.
• Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python).
• Experience with power‑aware verification methodologies and tools (e.g., UPF, CPF).
• Familiarity with performance verification techniques and metrics.
• Exposure to tools like Clearcase/Perforce and simulation/debug environments.
• Strong analytical, debugging, and communication skills.

About Company

ACL Digital, part of the ALTEN Group, is a trusted AI‑led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data‑powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Industries

Semiconductor Manufacturing

Location: Thiruporur, Tamil Nadu, India