GLS Verification Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru seeks a hardware verification engineer focused on gate-level simulations and pre-silicon signoff. You will execute GLS with zero-delay and SDF timing, debug setup/hold, recovery/removal, X-propagation, and timing violations, and validate RTL-to-gate equivalence.

You will perform SoC-level GLS for boot, reset, clocks and interrupts, verify low-power features (UPF, isolation, retention and level shifters), and validate DFT/scan/ATPG/JTAG at gate level.

Qualifications

• GlS / gate-level verification experience
• RTL-to-gate equivalence validation
• DFT/ATPG/JTAG familiarity
• SoC-level GLS exposure
• Low-power verification (UPF) experience

Responsibilities

• Execute gate-level simulations with zero-delay and SDF timing
• Debug setup/hold, recovery/removal, X-propagation, and timing violations
• Validate RTL-to-gate equivalence and synthesis/PD impacts
• Perform SoC-level GLS for boot, reset, clocks, interrupts
• Verify low-power features (UPF, isolation, retention, level shifters)
• Validate DFT/scan/ATPG/JTAG at gate level
• Debug failures using VCS/Xcelium/Questa and Verdi/DVE
• Correlate GLS failures with STA, RTL, synthesis, PD, and DFT
• Automate GLS regressions using Python/Perl/Tcl/Shell
• Support pre-silicon signoff and tape-out readiness

Skills

GLS expertise

RTL-to-gate

Timing verification

Low-power design

DFT/ATPG/JTAG

Regression automation

Python scripting

Verdi DVE

Tools

VCS/Xcelium/Questa

Verdi/DVE

Python

Perl

Tcl

Shell

Job description

• Execute Gate-Level Simulations (GLS) with zero-delay and SDF timing.
• Debug setup/hold, recovery/removal, X-propagation, and timing violations.
• Validate RTL-to-gate equivalence and synthesis/P&R impacts.
• Perform SoC-level GLS for boot, reset, clocks, interrupts, and functional scenarios.
• Verify low-power features such as UPF, isolation, retention, and level shifters.
• Validate DFT/scan/ATPG/JTAG functionality at gate level.
• Debug failures using VCS/Xcelium/Questa, Verdi/DVE and waveform analysis.
• Correlate GLS failures with STA, RTL, synthesis, PD, and DFT results.
• Automate GLS regressions using Python/Perl/Tcl/Shell.
• Support pre-silicon signoff and tape-out readiness.