GLS Verfication Engineer

Weekday AI (YC W21); Hyderabad; On-site; INR 2,000,000 - 8,000,000; Full time

Job summary

Weekday AI (YC W21) in Hyderabad is seeking a Design Verification Engineer – GLS to join our semiconductor verification team. You will lead gate-level and post-synthesis verification for complex SoC/ASIC designs, develop GLS environments, and work with SystemVerilog and UVM.

The role involves SDF-annotated timing simulations, cross-team collaboration with RTL, Synthesis, STA, Physical Design, and DFT, and driving regression suites to closure while improving verification methodologies.

Qualifications

• 2+ years of relevant experience in Design Verification
• Experience in GLS and post-synthesis verification
• Strong SystemVerilog and UVM proficiency
• Experience with SDF annotation and timing simulation
• Strong understanding of digital design, RTL, ASIC/SoC architecture
• Proven ability to debug complex GLS failures across RTL, netlists, constraints, libraries, and testbenches

Responsibilities

• Lead GLS and post-synthesis verification for complex SoC/ASIC designs.
• Develop, configure, execute, and debug gate-level simulation environments.
• Work extensively with SystemVerilog and UVM-based verification environments.
• Perform SDF-annotated timing simulations and analyse timing-related failures.
• Debug GLS failures across RTL, synthesized netlists, constraints, libraries, testbenches, and simulation configurations.
• Investigate functional, timing, reset, initialization, and X-propagation issues observed during gate-level simulation.
• Collaborate with RTL, Synthesis, STA, Physical Design, and DFT teams to identify and resolve root causes.
• Execute large-scale simulation and regression suites and analyse failures systematically.
• Track verification status, regression results, coverage, defects, and verification closure activities.
• Support verification of clock, resets, interfaces, and integration logic across design stages.

Skills

Gate-Level Simulation

SystemVerilog

UVM

SDF timing

Timing analysis

Python scripting

Regression management

Debug GLS

SoC/ASIC verification

Post-synthesis verification

Tools

VCS

Xcelium

Questa

Verdi

DVE

Job description

Job Description:

This role is for one of the Weekdays clients

Salary range: Rs 2000000 - Rs 8000000 (ie INR 20-80 LPA)

Experience: 2+ yrs

Location: Hyderabad, Telangana, India

Job Type: Full-time

As a Design Verification Engineer – GLS, you will work ongate-level and post-synthesis verificationof complex digital designs. You will develop, configure, execute, and debug GLS environments while analysing functional and timing-related failures.

A key part of the role will involveSDF-annotated simulations, where you will investigate timing behaviour and failures across different design stages. You will work closely with RTL, synthesis, Static Timing Analysis (STA), Physical Design, DFT, and other engineering teams to identify the source of issues and drive them through resolution.

You will also contribute to full-chip and subsystem-level verification, execute regression suites, analyse failures, track coverage, and support overall verification closure. The role provides an opportunity to work on complex SoC/ASIC designs and contribute to improving verification methodologies, automation, and debugging efficiency.

Key Responsibilities

• LeadGate-Level Simulation (GLS)and post-synthesis verification activities for complex SoC/ASIC designs.
• Develop, configure, execute, and debug gate-level simulation environments.
• Work extensively withSystemVerilog and UVM-based verification environments.
• PerformSDF-annotated timing simulationsand analyse timing-related failures.
• Debug GLS failures across RTL, synthesized netlists, constraints, libraries, testbenches, and simulation configurations.
• Investigate functional, timing, reset, initialization, and X-propagation issues observed during gate-level simulation.
• Collaborate withRTL, Synthesis, STA, Physical Design, and DFT teamsto identify and resolve root causes.
• Execute large-scale simulation and regression suites and analyse failures systematically.
• Track verification status, regression results, coverage, defects, and verification closure activities.
• Support bothfull-chip and subsystem-level verificationacross different stages of the design lifecycle.
• Analyse discrepancies between RTL and gate-level behaviour and drive appropriate fixes.
• Develop and maintain scripts and automation to improve regression execution and debugging efficiency.
• Support verification of complex SoC features, interfaces, clocks, resets, and integration logic.
• Contribute to verification methodologies, reusable environments, debugging practices, and process improvements.
• Document issues, root-cause analysis, verification results, and closure status.
• Support investigation of post-silicon issues by correlating silicon behaviour with simulation and verification results.

What Makes You a Great Fit

• 2+ years of relevant experiencein Design Verification, ASIC/SoC verification, or a closely related semiconductor engineering role.
• Strong hands-on experience withGate-Level Simulation (GLS)and post-synthesis verification.
• Strong proficiency inSystemVerilog and UVM.
• Practical experience withSDF annotation and timing simulation.
• Strong understanding of digital design, RTL, ASIC/SoC architecture, and verification methodologies.
• Proven ability to debug complex GLS failures across RTL, netlists, constraints, libraries, and testbench environments.
• Experience using industry-standard simulation and debugging tools such asVCS, Xcelium, Questa, Verdi, or DVE.
• Experience with regression management, failure analysis, coverage tracking, and verification closure.
• Strong analytical and problem-solving skills with attention to timing, initialization, reset, and integration issues.
• Good understanding of synthesis, STA, physical design, and DFT flows.
• Familiarity withSVA, CDC, reset verification, and low-power verification using UPFis an advantage.
• Experience withPython, Perl, or Shell scriptingfor verification automation is desirable.
• Exposure to full-chip SoC verification and analysis ofpost-silicon issueswill be an advantage.
• Strong communication and collaboration skills with the ability to work effectively across multidisciplinary semiconductor teams.
• Ability to take ownership of verification tasks, investigate complex failures independently, and drive issues through closure.