GLS verfication engineer

Weekday AI; Hyderabad; On-site; INR 200,000 - 800,000; Full time

Job summary

Weekday AI in Hyderabad, India is seeking a Design Verification Engineer – GLS to work on gate-level and post-synthesis verification of complex SoC/ASIC designs. You will develop, configure, execute, and debug GLS environments while analyzing functional and timing-related failures.

A key part of the role involves SDF-annotated simulations to investigate timing across design stages. You will collaborate with RTL, Synthesis, STA, Physical Design, DFT and other teams to identify root causes and

Qualifications

• 2+ years of experience in Design Verification, ASIC/SoC verification, or a closely related semiconductor role.
• Strong hands-on experience with Gate-Level Simulation (GLS) and post-synthesis verification.
• Strong proficiency in SystemVerilog and UVM.

Responsibilities

• Lead Gate-Level Simulation (GLS) and post-synthesis verification activities for complex SoC/ASIC designs.
• Develop, configure, execute, and debug gate-level simulation environments.
• Work extensively with SystemVerilog and UVM-based verification environments.
• Perform SDF-annotated timing simulations and analyse timing-related failures.
• Debug GLS failures across RTL, synthesized netlists, constraints, libraries, testbenches, and simulation configurations.
• Collaborate with RTL, Synthesis, STA, Physical Design, and DFT teams to identify and resolve root causes.
• Execute large-scale simulation and regression suites and analyse failures systematically.
• Track verification status, regression results, coverage, defects, and closure activities.
• Support full-chip and subsystem-level verification across design lifecycle.

Skills

Gate-Level Simulation

Post-synthesis verification

SystemVerilog

UVM

Debug GLS failures

RTL/SoC architecture

Tools

VCS

Xcelium

Questa

Verdi

DVE

SDF timing

Python scripting

Perl

Shell scripting

Job description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟬𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟴𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟬-𝟴𝟬 𝗟𝗣𝗔)

Experience: 2+ yrs

Location: Hyderabad, Telangana, India

Job Type: Full-time

As a Design Verification Engineer – GLS, you will work on gate-level and post-synthesis verification of complex digital designs. You will develop, configure, execute, and debug GLS environments while analysing functional and timing-related failures.

A key part of the role will involve SDF-annotated simulations, where you will investigate timing behaviour and failures across different design stages. You will work closely with RTL, synthesis, Static Timing Analysis (STA), Physical Design, DFT, and other engineering teams to identify the source of issues and drive them through resolution.

You will also contribute to full-chip and subsystem-level verification, execute regression suites, analyse failures, track coverage, and support overall verification closure. The role provides an opportunity to work on complex SoC/ASIC designs and contribute to improving verification methodologies, automation, and debugging efficiency.

Requirements

Key Responsibilities

• Lead Gate-Level Simulation (GLS) and post-synthesis verification activities for complex SoC/ASIC designs.
• Develop, configure, execute, and debug gate-level simulation environments.
• Work extensively with SystemVerilog and UVM-based verification environments.
• Perform SDF-annotated timing simulations and analyse timing-related failures.
• Debug GLS failures across RTL, synthesized netlists, constraints, libraries, testbenches, and simulation configurations.
• Investigate functional, timing, reset, initialization, and X-propagation issues observed during gate-level simulation.
• Collaborate with RTL, Synthesis, STA, Physical Design, and DFT teams to identify and resolve root causes.
• Execute large-scale simulation and regression suites and analyse failures systematically.
• Track verification status, regression results, coverage, defects, and verification closure activities.
• Support both full-chip and subsystem-level verification across different stages of the design lifecycle.
• Analyse discrepancies between RTL and gate-level behaviour and drive appropriate fixes.
• Develop and maintain scripts and automation to improve regression execution and debugging efficiency.
• Support verification of complex SoC features, interfaces, clocks, resets, and integration logic.
• Contribute to verification methodologies, reusable environments, debugging practices, and process improvements.
• Document issues, root-cause analysis, verification results, and closure status.
• Support investigation of post-silicon issues by correlating silicon behaviour with simulation and verification results.

What Makes You a Great Fit

• 2+ years of relevant experience in Design Verification, ASIC/SoC verification, or a closely related semiconductor engineering role.
• Strong hands-on experience with Gate-Level Simulation (GLS) and post-synthesis verification.
• Strong proficiency in SystemVerilog and UVM.
• Practical experience with SDF annotation and timing simulation.
• Strong understanding of digital design, RTL, ASIC/SoC architecture, and verification methodologies.
• Proven ability to debug complex GLS failures across RTL, netlists, constraints, libraries, and testbench environments.
• Experience using industry-standard simulation and debugging tools such as VCS, Xcelium, Questa, Verdi, or DVE.
• Experience with regression management, failure analysis, coverage tracking, and verification closure.
• Strong analytical and problem-solving skills with attention to timing, initialization, reset, and integration issues.
• Good understanding of synthesis, STA, physical design, and DFT flows.
• Familiarity with SVA, CDC, reset verification, and low-power verification using UPF is an advantage.
• Experience with Python, Perl, or Shell scripting for verification automation is desirable.
• Exposure to full-chip SoC verification and analysis of post-silicon issues will be an advantage.
• Strong communication and collaboration skills with the ability to work effectively across multidisciplinary semiconductor teams.
• Ability to take ownership of verification tasks, investigate complex failures independently, and drive issues through closure.