Full Chip RTL Design Architect

Mulya Technologies; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Mulya Technologies in Bengaluru is seeking a Senior Full Chip RTL Design Architect with deep expertise in RTL, SoC architecture, and full-chip implementations to define and execute RTL designs.

You will lead design methodology, collaborate with system architects, verification, physical design, and software teams, mentor engineers, and ensure designs meet timing, power, and quality targets. This role demands strategic thinking and hands-on leadership in a fast-paced environment.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 15+ years of RTL design, SoC architecture, and integration experience.
• Proven experience in full chip-level design for complex SoCs.
• In-depth knowledge of RTL design languages such as Verilog and SystemVerilog.
• Experience with low-power design techniques and power optimization.
• Familiarity with synthesis, timing analysis, and simulation; design-for-test (DFT) and design-for-debug (DFD) knowledge.

Responsibilities

• Define and develop full chip architecture and RTL designs for complex SoCs.
• Drive top-level integration of IPs and subsystems into full chip designs.
• Develop and optimize RTL design methodologies to improve quality, performance, and power efficiency.
• Lead RTL design reviews and provide technical guidance to design teams.
• Ensure compliance with coding standards, quality metrics, and verification requirements.
• Collaborate with system architects, verification engineers, physical design teams, and software developers to align design specifications and deliverables.

Skills

RTL Design

SoC Architecture

Verilog

Low-Power

Timing Analysis

Debugging

DFT/DFD

Physical Constraints

Education

Bachelors/Master in Electrical or Computer Engineering

Tools

Synopsys

Cadence

Mentor Graphics

HLS

Job description

Among. The top 4 IT companies, in India ranked by market capitalization and revenue

Job Description: Full Chip RTL Design Architect

We are seeking a highly skilled and experienced Full Chip RTL Design Architect to join our dynamic team. This role requires a deep understanding of RTL (Register-Transfer Level) design, SoC (System-on-Chip) architecture, and a passion for innovation in semiconductor design. The ideal candidate will play a critical role in defining and implementing full chip-level RTL designs and ensuring their successful execution.

Key Responsibilities

1. RTL Architecture and Design:

• Define and develop full chip architecture and RTL designs for complex SoCs.
• Drive the top-level integration of IPs and subsystems into full chip designs, ensuring design quality and efficiency.
• Collaborate on micro-architectural specifications and ensure seamless implementation.

2. Design Methodology and Implementation:

• Develop and optimize RTL design methodologies to improve quality, performance, and power efficiency.
• Lead RTL design reviews and provide technical guidance to design teams.
• Ensure compliance with coding standards, quality metrics, and verification requirements.

3. Cross-Functional Collaboration:

• Work closely with system architects, verification engineers, physical design teams, and software developers to align design specifications and deliverables.
• Provide feedback and solutions to cross-functional teams to resolve design challenges at all levels of the chip hierarchy.

4. Technical Leadership:

• Mentor and guide junior RTL engineers and team members, fostering a culture of technical excellence.
• Stay updated with advancements in RTL design tools, methodologies, and technologies to improve design practices.

5. Verification and Validation:

• Support pre-silicon verification efforts and collaborate with verification engineers to develop comprehensive test plans.
• Analyze simulation results, debug issues, and ensure that the design meets all functional, timing, and power requirements.

6. Performance Optimization:

• Identify and resolve bottlenecks in design performance, power, and area (PPA).
• Perform trade-off analysis and optimize designs for efficiency at the system level.

Required Qualifications

• - Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• - Experience:
• - 15+ years of experience in RTL design, SoC architecture, and integration.
• - Proven experience in full chip-level design for complex SoCs.
• - Technical Expertise:
• - In-depth knowledge of RTL design languages such as Verilog and SystemVerilog.
• - Experience with low-power design techniques and power optimization.
• - Expertise in debugging tools, synthesis, timing analysis, and simulation.
• - Familiarity with design-for-test (DFT), design-for-debug (DFD), and physical design constraints.
• - Problem-Solving Skills:
• - Strong analytical and debugging skills, with the ability to resolve complex technical issues.
• - Communication Skills:
• - Excellent verbal and written communication skills, with the ability to collaborate effectively across teams.

Preferred Qualifications

• - Advanced Degree: A Master’s or Ph.D. in Electrical or Computer Engineering.
• - Certifications: Relevant certifications in SoC architecture or design tools.
• - Familiarity with tools like Synopsys, Cadence, or Mentor Graphics for RTL and synthesis.
• - Experience with high-level synthesis (HLS) tools is a plus.
• - Industry Knowledge: Experience with the latest industry trends in AI, automotive SoCs, or 5G systems.