Digital Mixed Signal Engineer

Myraid; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Lead full-chip mixed-signal verification of SoCs in Bengaluru, applying Verilog-AMS/real-number modeling for ADC, DAC, PLL, bandgap and SerDes. Develop SV/UVM testbenches, drive coverage closure, and debug analog-digital issues.

Candidate should have BE/B.Tech/M.Tech in Electronics/VLSI with 5-10 years in mixed-signal verification and strong skills in Python/TCL scripting and debugging.

Qualifications

• B.E./B.Tech./M.Tech in Electronics/VLSI required.
• 5-10 years of experience in mixed-signal verification.
• Strong in Verilog-AMS, SystemVerilog/UVM, ADC/DAC, PLL and SerDes.
• Proficient in Python/TCL scripting and debugging.

Responsibilities

• Lead full-chip mixed-signal verification of SoCs.
• Build Verilog-AMS/real-number models for ADC, DAC, PLL, bandgap and SerDes.
• Develop SV/UVM testbenches, drive coverage closure, debug analog-digital issues.
• Automate regressions and workflows using Python/TCL.

Skills

Verilog-AMS

SystemVerilog/UVM

ADC/DAC

PLL

SerDes

Python scripting

TCL scripting

Debugging

Education

B.E./B.Tech./M.Tech in Electronics/VLSI

Job description

Lead full-chip mixed-signal verification of SoCs. Build Verilog-AMS/real-number models for ADC, DAC, PLL, bandgap and SerDes. Develop SV/UVM testbenches, drive coverage closure, debug analog-digital issues, automate regressions in Python/TCL.

Required Candidate profile

B.E/B.Tech/M.Tech in Electronics/VLSI with 5-10 yrs in mixed-signal verification. Strong in Verilog-AMS, SystemVerilog/UVM, ADC/DAC, PLL, SerDes. Python/TCL scripting. Strong debug skills.