Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457)

Source-Right; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Source-Right is seeking a Mixed-Signal Co-Simulation Engineer to drive full-chip and block-level verification using Cadence AMS Designer/Xcelium or Synopsys VCS. You will build behavioral analog models and verify interfaces across analog and digital blocks.

Join a team that develops RNM/wreal models, uses Python/Perl/Tcl for automation, and works on mixed-signal/AMS verification and coverage.

Qualifications

• Must have SystemVerilog, UVM, Verilog, Verilog-AMS, and RNM (wreal).
• Experience with mixed-signal verification and co-simulation.
• Knowledge of PLL, DLL, DCC, ADC, DAC, LDO, Bandgap, and ZQ calibration.
• Strong hands-on experience in mixed-signal/AMS verification.

Responsibilities

• Run full-chip or block-level mixed-signal co-simulations with Cadence AMS Designer/Xcelium or Synopsys VCS.
• Develop behavioral analog models using Verilog-AMS, Verilog, and SystemVerilog RNM/wreal.
• Build metric-driven verification environments using SystemVerilog and UVM-AMS.
• Debug analog/digital interface issues, waveform anomalies, convergence, and coverage.
• Develop automation scripts in Python, Perl, or Tcl for flows and reporting.
• Create and execute verification plans to validate models against transistor-level schematics.
• Configure mixed-mode simulations with blocks at schematic/SPICE level and others as behavioral.

Skills

SystemVerilog

UVM

Verilog

Verilog-AMS

SystemVerilog RNM (wreal)

Mixed-signal verification

Co-simulation experience

Tools

Cadence Virtuoso

Spectre

Xcelium

Cadence AMS Designer

Synopsys VCS

Job description

Position: Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457)

Key Responsibilities

• Run full-chip or block-level mixed-signal co-simulations using Cadence AMS Designer/Xcelium or Synopsys VCS.
• Develop behavioral analog models using Verilog-AMS, Verilog, and SystemVerilog Real Number Modeling (RNM/wreal).
• Build metric-driven verification environments using SystemVerilog and UVM-AMS.
• Debug analog and digital interface issues, waveform anomalies, simulation convergence failures, and drive functional coverage closure.
• Develop automation scripts in Python, Perl, or Tcl for verification flows, regression management, and reporting.
• Create and execute verification plans to validate behavioral models against transistor-level schematics.
• Configure and execute mixed-mode simulations with selected blocks running at schematic/SPICE level while the remaining design uses behavioral models.

Required Skills And Qualifications

• SystemVerilog, UVM, Verilog, Verilog-AMS, and SystemVerilog RNM (wreal)
• Mixed-signal verification and co-simulation experience
• Knowledge of PLL, DLL, DCC, ADC, DAC, LDO, Bandgap, and ZQ Calibration
• Experience with Cadence Virtuoso, Spectre, Xcelium, Cadence AMS Designer, or Synopsys VCS
• Strong hands‑on experience in mixed-signal/AMS verification.