Analog Mixed Signal Verification

Connectpro Management Consultants; Bengaluru; Vor Ort; INR 3.500.000 - 5.500.000; Vollzeit

Zusammenfassung

Connectpro Management Consultants seeks a Lead for Analog/Mixed-Signal Design Verification with 9–16 years of experience to head a verification team in Bengaluru. The role focuses on AMS functional verification, DV methodologies, test planning, and coverage closure for pre-silicon verification of AMS/IPs such as SERDES and sensors.

The candidate will guide the DV group, coordinate with digital and analog teams, and help drive continuous DV process improvements for high-quality silicon products.

Qualifikationen

• BS degree with extensive experience in AMS/FV
• MS degree with substantial relevant industry experience
• 9+ years in ASIC functional verification or related field

Aufgaben

• Verify AMS IPs and SERDES designs in a UVM-based environment
• Lead a Design Verification group, plan schedules and allocate resources
• Develop scalable test benches, drivers, checkers, and reference models
• Collaborate with global teams for DV capabilities and process improvements

Kenntnisse

UVM

SystemVerilog

SVA

AMS DV

Test bench

Code coverage

Perforce

Leadership

Verilog

Python

Ausbildung

BS degree

MS degree

Tools

Verilog

SystemVerilog

UVM

Scripting (Python)

Jobbeschreibung

Analog/Mixed-Signal Design Verification- Lead (9 to 16 years)

Work on Analog/Mixed-Signal Functional Verification for Analog/Mixed-Signal IPs, such as SERDES, Sensors and beyond. The candidate will work as a Technical Lead for a group of engineers, who work with digital design, analog design, analog behavioral modeling and other design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to the entire life cycle of AMS Functional Verification process, from understanding specification, test planning to coverage closure and post silicon debugging support, to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.

Skills/Experience

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, digital design and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers, and checkers development, to test suite building to meet functional and code coverage goals,
• 3+ year Experience as Technical Lead of a Design Verification group/team is preferred.
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
• Power-aware simulations and gate level simulations is a plus
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus
• Familiar with programming languages: C, C++, and/or SystemC is a plus.

Responsibilities

• Work in AMS IP Design Verification, in UVM-based verification environment.
• Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
• Act as Technical Lead of a Design Verification group/team by providing technical guidance, planning schedule and resource to meet requirement for project deliverables, fostering methodology advancement, and so on.
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.

Education Requirements

• BS degree and a minimum of 9 years of relevant industry experience, or
• MS degree with a minimum of 6 years of relevant industry experience
• Senior positions to be offered to candidates with proven expertise in the relevant field