DFT Lead / Manager

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru is seeking an experienced DFT Lead to own end-to-end design for test of complex SoCs and drive delivery.

This role combines hands-on DFT mastery with team leadership across RTL, verification and physical design to ensure robust testability and efficient problem resolution.

The ideal candidate has 8–18 years of experience, deep knowledge of Tessent, TestMAX or Modus, and strong communication for stakeholder coordination.

Qualifications

• BE/B.Tech/M.Tech in Electronics or related field.
• 8-18 years of DFT experience including technical leadership.
• Expertise in scan, ATPG, fault models, test coverage analysis, memory testing.
• Experience with Tessent, TestMAX, Modus.
• Proficiency in Verilog/SystemVerilog and scripting (Tcl, Python, Perl).
• Experience with multiple SoC tape-outs; strong debugging and communication skills.
• Techno-managerial roles: leading teams and owning project delivery.

Responsibilities

• Define and implement DFT architecture including scan insertion, compression, ATPG, MBIST and JTAG/boundary scan.
• Drive test coverage closure, pattern generation, simulation and debugging.
• Collaborate with RTL, verification, physical design and test teams to resolve DFT issues.
• Support silicon bring-up, ATE pattern debugging and diagnosis.
• Review technical deliverables, mentor engineers and ensure DFT milestones meet quality standards.
• For techno-managerial roles, manage resource planning, schedules, delivery risks and stakeholder communication.

Skills

Technical leadership

DFT expertise

ATPG

Scan methodologies

Team leadership

Communication

Verilog/SystemVerilog

Tcl/Python

Education

B.E./B.Tech/M.Tech in Electronics/Electrical Engineering or related

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

Hiring: DFT Lead / Techno-Managerial Engineer

Location: Bangalore | Experience: 8-18 years

Role Overview

Lead end-to-end Design for Test (DFT) activities for complex SoC designs, combining hands-on technical ownership with team leadership and project delivery.

Key Responsibilities

• Define and implement DFT architecture, including scan insertion, compression, ATPG, MBIST and JTAG/boundary scan.
• Drive test coverage closure, pattern generation, simulation and debugging.
• Collaborate with RTL, verification, physical design and test teams to resolve DFT integration, timing and testability issues.
• Support silicon bring-up, ATE pattern debugging and diagnosis.
• Review technical deliverables, mentor engineers and drive quality across DFT milestones.
• For techno-managerial roles, manage resource planning, schedules, delivery risks and stakeholder communication.

Required Skills & Qualifications

• B.E./B.Tech/M.Tech in Electronics, Electrical Engineering or a related discipline.
• 8-18 years of relevant DFT experience, including technical leadership.
• Strong expertise in scan methodologies, ATPG, fault models, test coverage analysis and memory testing.
• Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX or Cadence Modus.
• Proficiency in Verilog/SystemVerilog and scripting using Tcl, Python or Perl.
• Experience with multiple SoC tape-outs and strong debugging, problem-solving and communication skills.
• For techno-managerial positions, proven experience leading teams and owning project delivery.