DFT Design Engineer

Intel Corporation; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Intel Corporation in Bengaluru seeks a highly experienced DFT Design Engineer to design, implement, and validate DFT solutions across IP and SoC programs. You will develop TAP/JTAG, IJTAG, boundary scan, MBIST, and ATPG patterns while driving test access and coverage improvements.

The role requires RTL/GLS validation, silicon debug, and leadership in reviews and process improvements with strong communication.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or related field with 10+ years of experience.
• Master's degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.
• Scan Insertion, DFT features, RTL design for DFT and verification.

Responsibilities

• Design, implement, validate, and debug DFT solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
• Develop and validate TAP/JTAG, IJTAG infrastructures, Boundary Scan, MBIST, and related test collateral (ICL, PDL, BSDL, ATPG patterns).
• Drive test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues; ensure robust DFT integration across the product lifecycle.
• Collaborate with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.

Skills

TAP/JTAG

IJTAG (IEEE 1687)

Boundary Scan (IEEE 1149.1)

MBIST

ATPG

Scan Compression

Verilog/SystemVerilog

Tcl/Perl/Python scripting

DFT verification

Silicon debug

Communication & leadership

Education

Bachelor's Degree in Electrical/Electronics/CS

Master's Degree in Electrical/Microelectronics/VLSI

Job description

## DFT Design EngineerApplylocations: India, Bangaloretime type: Full timeposted on: Posted Todayjob requisition id: JR0286042# **Job Details:**## Job Description:* Design, implement, validate, and debug Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.* Responsibilities include development and validation of TAP/JTAG and IJTAG infrastructures, Boundary Scan (BSCAN), MBIST, Scan/ATPG methodologies, and associated test collateral such as ICL, PDL, BSDL, and ATPG patterns. The role requires driving test access, pattern generation, coverage optimization, memory test validation, and debug of scan, at-speed, and silicon bring-up issues while ensuring robust DFT integration across the product lifecycle.* The engineer collaborates closely with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.* Key responsibilities include RTL and Gate-Level Simulation (GLS) validation, root-cause analysis and resolution of DFT-related failures, adoption of DFT methodologies and best practices, and leadership of technical reviews and continuous process improvements.* Required expertise includes TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, Scan Compression, ATPG, Verilog/System Verilog, Tcl/Perl/Python scripting, DFT verification, silicon debug, and strong communication and technical leadership skills.## **Qualifications:*** Candidate must have a Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience Or* Master's Degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.* Scan Insertion, DFT features, RTL design for DFT and verification.## Job Type:Experienced Hire## Shift:Shift 1 (India)## Primary Location:India, Bangalore## Additional Locations:## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change.