DFT Engineer/Senior DFT Engineer

Qiskitq Technology; Bengaluru; Hybrid; INR 1,800,000 - 3,000,000; Full time

Job summary

QiskitQ Technology is seeking experienced DFT Engineers to drive end-to-end DFT for production SoCs. You will lead scan insertion, ATPG coverage, and MBIST integration across blocks and full-chip designs.

Candidates should have 5+ years in DFT, and hands-on experience with Siemens Tessent, Synopsys DFT tools, Cadence Modus, and multiple simulators. Hybrid/remote in India options available.

Qualifications

• 5+ years of hands-on DFT experience on production SoCs/ASICs.
• End-to-end scan insertion and ATPG coverage closure experience.
• MBIST implementation and debugging for embedded memories; JTAG/boundary scan.
• Proficiency in Tcl; Python or Perl scripting in test flow.
• Experience with industry tools: Tessent, Synopsys DFT tools, Cadence Modus, simulators.

Responsibilities

• Define and implement robust DFT architecture and test strategies for blocks and full-chip SoCs.
• Handle scan insertion, test compression (EDT / DFTMAX / OCC), and resolve DRC violations.
• Generate ATPG patterns for stuck-at, transition, and path-delay faults for high coverage.
• Implement and verify MBIST and repair (BISR) for embedded memories; work with JTAG/IJTAG networks.
• Drive gate-level simulations (with/without timing) and collaborate with STA, physical design, and ATE teams.

Skills

End-to-end scan insertion

ATPG coverage

MBIST implementation

JTAG/boundary scan

Gate-level simulation

Tcl scripting

Python/Perl scripting

Education

B.E./B.Tech in Electronics

M.Tech in Electronics

Tools

Siemens Tessent

Synopsys DFT tools (DFT Compiler / TestMAX / TetraMAX)

Cadence Modus

VCS / Xcelium / Questa

Job description

DFT Engineers / Senior DFT Engineers!

Are you passionate about taking complex SoCs from RTL all the way to silicon? QiskitQ is hiring DFT Engineers (5 to 10 years of experience) for a leading semiconductor client! If you have deep expertise in scan, ATPG, and MBIST, we want to talk to you.

Role Overview

• Role: DFT Engineer / Senior DFT Engineer
• Experience: 310 years in DFT
• Location: Bengaluru / Kolkata / Pune (Hybrid / Remote options available)
• Engagement: Full-time (Multiple positions open!)
• Notice Period: Immediate to 30 days preferred

What You will Do

• Define and implement robust DFT architecture and test strategies for blocks and full-chip SoCs.
• Handle scan insertion, test compression (EDT / DFTMAX / OCC), and resolve DRC violations.
• Generate ATPG patterns for stuck-at, transition, and path-delay faults to achieve 99%+ test coverage.
• Implement and verify MBIST and repair (BISR) for embedded memories, alongside JTAG and IJTAG networks.
• Drive gate-level simulations (with and without timing) and collaborate with STA, physical design, and ATE teams for seamless silicon bring-up and debug.

What We Are Looking For

• Education: B.E. / B.Tech / M.Tech in Electronics, Electrical, or VLSI.
• Experience: 5+ years of hands-on DFT experience on production SoCs/ASICs (junior/senior brackets welcome across the 310 year spectrum).
• Core Skills: End-to-end scan insertion & ATPG coverage closure, MBIST implementation/debug, JTAG/boundary scan, and gate-level simulation.
• Scripting: Strong proficiency in Tcl, plus Perl or Python.
• Tools Knowledge: Siemens Tessent, Synopsys (DFT Compiler / TestMAX / TetraMAX), Cadence Modus, and simulators like VCS, Xcelium, or Questa.
• Bonus points for silicon bring-up, ATE debug, hierarchical DFT, LBIST, test-mode STA, or advanced node experience (7nm and below)!