DFT Engineer

Erbity Private Limited; Pune District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity Private Limited in Pune, India, seeks a Senior DFT Engineer to architect, implement, and validate DFT methods for complex SoCs/ASICs, ensuring manufacturability and reliable silicon bring-up. You will lead scan insertion, ATPG, MBIST, and test pattern validation while collaborating with RTL, verification, and physical design teams.

A BS/MS in Electrical Engineering or Microelectronics and 5–8 years in DFT are required; scripting in Python/Perl/TCL is essential.

Qualifications

• BS/MS in Electrical Engineering or Microelectronics required.
• 5–8 years of experience in DFT for complex SoCs/ASICs.
• Experience with scan insertion, ATPG, MBIST, boundary scan, and JTAG.

Responsibilities

• Define and implement DFT methodologies for SoCs, MCUs, or test chips.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Architect innovative DFT techniques for advanced process nodes.

Skills

DFT knowledge

ATPG

MBIST

Scan insertion

Boundary scan

JTAG

Scripting (Python, Perl, TCL)

Education

Electrical Engineering / Microelectronics (B.E./B.Tech or M.E./M.Tech)

Tools

Python

Perl

TCL

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Debug test pattern issues during silicon bring-up.
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams.
• Support silicon characterization and yield improvement activities.
• Contribute to overall microcontroller or SoC DFT methodology.
• Bachelor's/master's in electrical engineering, Microelectronics, or related field.
• Typically, 5-8 years in DFT for complex SoCs/ASICs.
• Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG.
• Debugging silicon test issues and yield analysis.
• Experience in Scripting/ programming using Python, Perl, TCL.