DFT Engineer

Erbity; Hyderabad; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Erbity is seeking a Senior DFT Engineer to architect, implement, and validate test methodologies for complex SoCs/ASICs, ensuring manufacturability and reliable silicon bring-up.

You will lead scan insertion, ATPG, MBIST, and test pattern validation while collaborating with RTL, verification, and physical design teams to optimize yield and test coverage.

Applicants should have 5–8 years in DFT and proficiency in Python/Perl/TCL for scripting.

Qualifications

• 5–8 years of experience in DFT for complex SoCs/ASICs.
• Experience with scan insertion, ATPG, MBIST, boundary scan, and JTAG.
• Proficient in Python, Perl, TCL scripting for automation.

Responsibilities

• Define and implement DFT methodologies for SoCs/MCUs.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Generate ATPG patterns and debug test pattern issues during bring-up.
• Collaborate with RTL, verification, physical design, and test teams.

Skills

Test pattern development

Debugging silicon issues

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Python

Perl

TCL

JTAG

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck-at, transition, and path delay faults
• Debug test pattern issues during silicon bring-up
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams
• Support silicon characterization and yield improvement activities
• Contribute to overall microcontroller or SoC DFT methodology
• Bachelor's/master's in electrical engineering, Microelectronics, or related field

Requirements

• Typically, 5-8 years in DFT for complex SoCs/ASICs
• Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG
• Debugging silicon test issues and yield analysis
• Experience in Scripting/ programming using Python, Perl, TCL