DFT Engineer

Erbity Private Limited; Ahmedabad District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity Private Limited seeks a Senior DFT Engineer to architect, implement, and validate test methodologies for complex SoCs/ASICs, ensuring manufacturability and reliable silicon bring-up. Lead scan insertion, ATPG, MBIST, and test pattern validation across RTL, verification, and physical design teams.

Develop DFT techniques for advanced nodes, generate and debug patterns for stuck-at and path faults, and partner with cross-functional teams to optimize yield and test coverage.

Qualifications

• Bachelor's/Master's in Electrical Engineering or Microelectronics is required.
• Experience with DFT for complex SoCs/ASICs.
• Strong scripting and debugging skills for test patterns and yield analysis.

Responsibilities

• Define and implement DFT methodologies for SoCs/ASICs.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Generate ATPG patterns and validate test coverage on ATE.

Skills

DFT techniques

Scan insertion

ATPG

MBIST

Boundary scan

JTAG

Python

Perl

TCL

Yield analysis

Education

Electrical Engineering or Microelectronics

Tools

Python

Perl

TCL

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Debug test pattern issues during silicon bring-up.
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams.
• Support silicon characterization and yield improvement activities.
• Contribute to overall microcontroller or SoC DFT methodology.
• Bachelor's/master's in electrical engineering, Microelectronics, or related field.
• Typically, 5-8 years in DFT for complex SoCs/ASICs.
• Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG.
• Debugging silicon test issues and yield analysis.
• Experience in Scripting/ programming using Python, Perl, TCL.