Tcs Hiring For Senior DFT Engineer/Lead

Tata Consultancy Services; Bengaluru; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

Tata Consultancy Services in Bengaluru, India, is seeking a Senior DFT Engineer/Lead to architect and implement DFT strategies for advanced Custom SoC designs. You will collaborate with Design, Verification and Implementation teams to ensure DFT requirements are met and mentor junior engineers.

The role involves hands-on DFT work including scan insertion, ATPG, JTAG/LBIST, DRC, and coverage analysis, plus post-silicon readiness and silicon debugging.

Qualifications

• Proficient in Verilog/VHDL RTL coding for complex SoCs.
• Hands-on experience with scan insertion, JTAG, LBIST, ATPG, DRC, and coverage analysis.
• Experience with post-silicon readiness, pattern generation and silicon debugging.

Responsibilities

• Architect and implement DFT strategies for advanced Custom SoC designs.
• Collaborate with Design, Verification and Implementation teams to meet DFT requirements.
• Perform scan insertion, ATPG pattern generation, and LBIST/Memory and Logic BIST implementation.
• Debug and resolve DFT-related issues throughout the design process.
• Mentor junior engineers and provide technical guidance.

Skills

Verilog/VHDL RTL coding

DFT strategy design

Mentoring

Test time optimization

Tools

Mentor DFT

Cadence tools

Synopsys EDA tools

JTAG

LBIST

ATPG

Job description

Role : Senior DFT Engineer/Lead

Required Technical Skill Set :

Architect and implement DFT strategies for advanced Custom SoC designs. Collaborate with Design, Verification and Implementation teams to ensure DFT requirements are met. Perform scan insertion, ATPG pattern generation, and BIST (Memory and Logic) implementation. Perform DFT simulations and analyze results to ensure test coverage and quality. Debug and resolve DFT-related issues throughout the design process. Mentor junior engineers and provide technical guidance as needed. Identify Test time optimization opportunities.

Must-Have**

Well versed in Verilog/VHDL RTL coding, experienced in using Mentor DFT, Cadence and Synopsys EDA tools. Hands‑on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Must have worked on few SoC DFT effort at least, from start to end. Must be proactive, collaborative and detail-oriented capable of exercising independent judgment. Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug.

Good to Have

Excellent understanding of logic design fundamentals and gate/transistor level implementation. Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions. Strong problem solving and debug skills across various levels of design hierarchies.