DFT Engineer

ASIP Technologies; Hyderabad; On-site; INR 1,800,000 - 2,700,000; Full time

Job summary

ASIP Technologies in Hyderabad is seeking a DFT Engineer to design, implement, and validate DFT structures for complex SoC designs. This full-time, on-site role collaborates with RTL Design, Verification, BE Implementation and Test Engineering.

You will drive insertion and verification of TAP/Scan architectures, Scan Synthesis, ATPG and coverage analysis, and work with Frontend Design, Physical Design and timing teams to resolve DFT issues and improve test patterns.

Qualifications

• 5+ years of industry experience in DFT
• Strong skills in DFT architecture and concepts with hands-on implementation and verification
• Deep understanding of TAP, JTAG, Scan Architecture, Scan Synthesis, ATPG, and related areas
• Experience with ATE, test program development, scripting, and data analysis tools preferred
• Bachelor's or Master's degree in Electrical/ Electronics/ Computer Engineering or related field

Responsibilities

• Design, implement, and validate DFT structures for complex SoC designs
• Insertion and verification of TAP/Scan architecture and related patterns
• Scan synthesis, ATPG execution, and coverage analysis
• Collaborate with Frontend, Verification, Physical Design, and Timing teams
• Develop and review Test Plans and optimize Test Programs

Skills

DFT Architecture & Concepts

ATPG & Pattern Generation

TAP / JTAG / Scan Architecture

Scan Synthesis

Low Coverage Debug & Memory BIST

Scripting: Python & TCL

Education

B.E./B.Tech in EE/ECE/CS

M.E./M.Tech in related field

Tools

Python

TCL

EDA Tools

Job description

The DFT Engineer role at ASIP Technologies is a full-time, on-site position based in Hyderabad. The DFT Engineer will design, implement, and validate DFT structures for complex SoC designs, collaborating with RTL Design, Verification, BE Implementation and Test Engineering teams.

Day-to-day responsibilities include Insertion and Verification of DFT structures (including TAP/Scan Architecture, JTAG, MBIST, etc.), Scan Synthesis, ATPG Execution, Scan Coverage Analysis. The role includes cross-functional collaboration with Frontend Design, Verification, Physical Design, Timing closure teams to resolve all DFT-related issues and contribute to the continuous improvement of the quality of the Test patterns. The role also includes developing and reviewing Test Plans, generating and optimizing Test Program, enabling Structural Test coverage and supporting Test Bringup on ATE.

Qualifications

• Atleast 5 years of Industry Experience with relevant skills
• Candidates should possess strong skills in DFT Architecture and Concepts with hands-on experience in Implementation, Verification, Pattern Generation and Simulation of all DFT structures
• Candidates should possess deep understanding of TAP, JTAG, Scan Arch, Scan Synthesis, ATPG, Low Coverage Debug, Memory BIST & Boundary Scan
• Experience with ATE (Automated Test Equipment), Test Program Development, Scripting (e.g., Python, TCL), and data analysis tools is preferred
• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field is required
• Ability to collaborate in cross-functional teams, communicate clearly and work systematically
• Familiarity with multiple industry-standard EDA tools and version control systems is preferred