DFT Engineer

Erbity; Chennai District; On-site; INR 1,600,000 - 3,000,000; Full time

Job summary

Erbity is seeking a Senior DFT Engineer to architect, implement, and validate test methodologies for complex SoC/ASIC designs, ensuring manufacturability and reliable silicon bring-up.

You will collaborate with RTL, verification and physical design teams, define DFT strategy, apply scan insertion, ATPG, MBIST and boundary scan, and develop robust test patterns using Python/Perl/TCL on-site in Chennai.

Qualifications

• 5–8 years in DFT for complex SoCs/ASICs.
• Experience in scan insertion, ATPG, MBIST, boundary scan, JTAG.
• Debugging silicon test issues and yield analysis.
• Scripting/programming using Python, Perl, TCL.

Responsibilities

• Define and implement DFT methodologies for SoCs, MCUs, or test chips.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Architect innovative DFT techniques for advanced process nodes.
• Generate and validate test patterns for ATPG and MBIST.
• Collaborate with RTL, verification, physical design, and test engineering teams.

Skills

DFT expertise

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Scan insertion

ATPG

MBIST

Boundary scan

JTAG

Python

Perl

TCL

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck-at, transition, and path delay faults
• Debug test pattern issues during silicon bring-up
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams
• Support silicon characterization and yield improvement activities
• Contribute to overall microcontroller or SoC DFT methodology
• Bachelor's/master's in electrical engineering, Microelectronics, or related field

Requirements

• Typically, 5-8 years in DFT for complex SoCs/ASICs
• Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG
• Debugging silicon test issues and yield analysis
• Experience in Scripting/ programming using Python, Perl, TCL