Dft Engineer

Allegis Group; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Allegis Group in Bengaluru is seeking a DFT/ATPG specialist to contribute to Scan & ATPG, MBIST, and verification flows.

You will work with Siemens Tessent Tools, ICL, PDL, and IEEE1149.1/1687 standards to generate test patterns, analyze coverage, and debug timing and scan issues. Proficiency in TCL scripting is required, with hands-on RTL/DFT experience in a complex SoC environment.

Qualifications

• Experience with ATPG and SSN methodology.
• Experience in pattern generation using Stuck-at and transition fault patterns.
• Knowledge of scan coverage analysis and RTL debugging.
• Familiarity with DFT checks in RTL and debugging simulation failures.
• Strong TCL/scripting knowledge.

Responsibilities

• Develop ATPG patterns and verify coverage across scans and testbenches.
• Collaborate on MBIST insertion and verification within RTL flows.
• Debug timing and scan-related simulation failures and fix violations.

Skills

DFT concepts

Scan design

Tools

Siemens Tessent Tools

IEEE1149.1

IEEE1687

VCS

ICL

PDL

Job description

Scan & ATPG

• Strong understanding of Siemens Tessent Tools for ATPG with SSN methodology
• Experience in ICL, PDL, Stuck-at and transition fault pattern generation
• Good understanding on scan coverage and experience in carrying out coverage analysis.
• Experience in Timing and no Timing gate level simulations and debugging simulation failures.
• Experience in carrying out DFT DRC checks in RTL and analyzing the violations.
• Strong understanding of Scan structures, IEEE1148.1, IEEE1687, ATPG methodology and flow.
• Good understanding of timing constraints.. synthesis flow and scan insertion using DC/FC
• Strong TCL/scripting knowledge

MBIST

• Strong understanding of Siemens Tessent tools for MBIST insertion and verification
• Experience in MBIST insertion in RTL, pattern generation.
• Experience in ICL, PDL, IEEE1149.1, IEEE1687, MBIST verification and debugging simulation failures.
• Good understanding of MBIST algorithms, architecture, and diagnosis features
• Strong TCL/scripting knowledge

Verification

• Strong knowledge on ICL, PDL, IEEE1149.1, IEEE1687, Simulations tools such VCS
• Experience in creation of DFT test bench structures, verifying DFX structures in RTL and debugging simulation failures.
• Good understanding of DFT structures such as scan controller, OCC, EDT, JTAG, iJTAG, IOs, HSIO loopback, reset controller.
• Strong TCL/scripting knowledge