DFT Staff Engineer

Veedee Solutions LLP; Hyderabad; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Veedee Solutions LLP in Hyderabad is seeking a DFT Staff Engineer to design, implement, and sign off DFT architectures for complex SoCs/IPs, ensuring testability, high quality, and manufacturability while balancing coverage, performance, power, and cost.

You will drive DFT strategy, perform scan insertion and stitching, develop ATPG patterns, integrate MBIST/LBIST and boundary scan, and verify DFT timing with STA across RTL and gate levels; collaborate across RTL, PD, verification, and test

Qualifications

• Core technical skills include scan insertion, compression, ATPG and fault models, MBIST/LBIST, JTAG/boundary scan (IEEE 1149.1), RTL design and verification, STA and timing closure, and SoC design flow.
• Familiarity with toolchains such as Synopsys, Cadence, and Siemens (TestMAX, Tessent, Modus); plus simulation tools and scripting languages (TCL, Python, Perl).
• A BSEE/MSEE or equivalent is typically required with proven end-to-end DFT implementation and debugging experience.

Responsibilities

• Define and implement DFT architecture at block/IP or SoC level with specified test methodologies.
• Perform scan insertion and stitching; generate and simulate ATPG patterns; integrate MBIST/LBIST and boundary scan.
• Debug scan/ATPG issues and optimize fault coverage, pattern count, and test time.
• Run DFT verification and DRC checks; ensure clean DFT signoff with coverage, timing, and power impact.
• Collaborate with RTL Design, Physical Design, Verification, and Test Engineering to enable end-to-end DFT flows.
• Support post-silicon bring-up and debug to improve manufacturing coverage.

Skills

Scan insertion

ATPG

MBIST / LBIST

JTAG / Boundary Scan

RTL design and verification

STA / timing closure

SoC design flow

Toolchains (Synopsys/Cadence/Siemens)

TestMAX / Tessent / Modus

VCS

Python / TCL / Perl

Education

BSEE/MSEE or equivalent

Tools

TestMAX

Tessent

Modus

Synopsys tools

Cadence tools

Siemens tools

VCS

Job description

Job Summary

A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor designs are testable, high-quality, and manufacturable while balancing coverage, performance, power, and cost.

Key Responsibilities

1. DFT Architecture & Strategy: Define and implement DFT architecture at block/IP or SoC level. Specify test methodologies (scan, MBIST, boundary scan, compression). Ensure testability is built early into the RTL design flow. Balance trade-offs between coverage, area, power, and test time.
2. DFT Implementation: Perform scan insertion and stitching. Generate and simulate ATPG patterns. Integrate MBIST / LBIST / boundary scan. Develop and validate DFT timing constraints (STA). Execute DFT flows at RTL and gate level.
3. Test Coverage & Quality: Analyze and improve fault coverage. Debug scan/ATPG issues and resolve coverage holes. Optimize pattern count, test cost, and test time.
4. Verification & Signoff: Run DFT verification and DRC checks. Ensure clean DFT signoff, including coverage, timing, and power impact. Validate patterns using simulation and test tools. Support DFT integration guidelines at SoC level.
5. Cross-Functional Collaboration: Work with RTL Design, Physical Design (PD), Verification, and Test Engineering / ATE. Drive issue resolution across teams and ensure end-to-end execution of DFT flows.
6. Silicon Bring-up & Debug: Support post-silicon debug and yield improvement. Debug tester failures and improve manufacturing coverage. Assist customer or product teams during bring-up.

Required Skills & Expertise

Core Technical Skills Strong expertise in scan insertion and compression, ATPG and fault models, MBIST / LBIST, JTAG / Boundary Scan (IEEE 1149.1), RTL design and verification, STA and timing closure, and SoC design flow. Familiarity with tools such as Synopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus), simulation tools (VCS, etc.), and scripting languages (TCL, Python, Perl) is essential. A BSEE/MSEE or equivalent is typically required, along with proven experience in end-to-end DFT implementation and debugging.