DFT Staff Engineer

Veedee Solutions LLP; Navi Mumbai; Sur place; INR 2 500 000 - 4 500 000; Plein temps

Résumé du poste

Veedee Solutions LLP is seeking a DFT Staff Engineer to design, implement, and sign off DFT architecture for complex SoCs/IPs. You will ensure testability, quality, and manufacturability while balancing coverage, performance, power, and cost.

The role involves defining DFT strategies, implementing scan and MBIST/LBIST, and optimizing test patterns. Collaboration with RTL, PD, verification, and test teams is essential for end-to-end DFT execution.

Qualifications

• Experience in scan insertion and compression, ATPG and fault models.
• Knowledge of MBIST / LBIST and JTAG/Boundary Scan (IEEE 1149.1).
• RTL design and verification expertise; STA and timing closure.

Responsabilités

• Define and implement DFT architecture at block/IP or SoC level.
• Perform scan insertion and stitching; generate ATPG patterns.
• Analyze fault coverage; debug scan/ATPG issues and resolve coverage holes.
• Run DFT verification and DRC checks; ensure clean signoff.
• Collaborate with RTL, PD, Verification, and Test Engineering / ATE.
• Support post-silicon bring-up and yield improvement.

Connaissances

Scan insertion

ATPG

MBIST/LBIST

Boundary Scan

RTL design

STA

Timing closure

SoC design flow

TCL

Python

VCS

Formation

BSEE/MSEE or equivalent

Outils

Synopsys tools

Cadence tools

Siemens tools (Tessent)

TestMAX

Tessent

VCS

Description du poste

Job Summary

A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor designs are testable, high-quality, and manufacturable while balancing coverage, performance, power, and cost.

Key Responsibilities

1. DFT Architecture & Strategy: Define and implement DFT architecture at block/IP or SoC level. Specify test methodologies (scan, MBIST, boundary scan, compression). Ensure testability is built early into the RTL design flow. Balance trade-offs between coverage, area, power, and test time.
2. DFT Implementation: Perform scan insertion and stitching. Generate and simulate ATPG patterns. Integrate MBIST / LBIST / boundary scan. Develop and validate DFT timing constraints (STA). Execute DFT flows at RTL and gate level.
3. Test Coverage & Quality: Analyze and improve fault coverage. Debug scan/ATPG issues and resolve coverage holes. Optimize pattern count, test cost, and test time.
4. Verification & Signoff: Run DFT verification and DRC checks. Ensure clean DFT signoff, including coverage, timing, and power impact. Validate patterns using simulation and test tools. Support DFT integration guidelines at SoC level.
5. Cross-Functional Collaboration: Work with RTL Design, Physical Design (PD), Verification, and Test Engineering / ATE. Drive issue resolution across teams and ensure end-to-end execution of DFT flows.
6. Silicon Bring-up & Debug: Support post-silicon debug and yield improvement. Debug tester failures and improve manufacturing coverage. Assist customer or product teams during bring-up.

Required Skills & Expertise

Core Technical Skills Strong expertise in scan insertion and compression, ATPG and fault models, MBIST / LBIST, JTAG / Boundary Scan (IEEE 1149.1), RTL design and verification, STA and timing closure, and SoC design flow. Familiarity with tools such as Synopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus), simulation tools (VCS, etc.), and scripting languages (TCL, Python, Perl) is essential. A BSEE/MSEE or equivalent is typically required, along with proven experience in end-to-end DFT implementation and debugging.