DFT Staff Engineer

Veedee Solutions LLP; Chennai; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Veedee Solutions LLP in Chennai seeks a DFT Staff Engineer to design and sign off DFT architectures for complex SoCs/IPs. You will balance coverage, performance, power, and cost while integrating MBIST/LBIST and boundary scan. Strong RTL experience is required.

The role involves collaboration across RTL, PD, verification, and test teams, plus post-silicon bring-up support to improve yield and manufacturability.

Qualifications

• Experience in scan insertion, compression, ATPG, and fault models.
• Familiar with MBIST/LBIST, JTAG and boundary scan (IEEE 1149.1).
• Proven RTL design, verification, STA timing closure in SoC flows.
• Experience with CAD/EDA tools and scripting languages.

Responsibilities

• Define and implement DFT architecture at block/SoC level.
• Perform scan insertion and stitching; generate ATPG patterns.
• Analyze fault coverage and optimize DFT test time.
• Run DFT verification and signoff with timing and power checks.
• Collaborate with RTL, PD, verification, and test teams.
• Support post-silicon bring-up and yield improvement.

Skills

Scan insertion

ATPG & fault models

MBIST / LBIST

JTAG/Boundary Scan

RTL design & verification

STA & timing closure

SoC design flow

EDA tools: TestMAX/Tessent/Modus

Simulation tools: VCS

Scripting: TCL, Python, Perl

Education

BSEE/MSEE or equivalent

Tools

TestMAX

Tessent

Modus

Synopsys

Cadence

Siemens tools

VCS

Job description

Job Summary

A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor designs are testable, high-quality, and manufacturable while balancing coverage, performance, power, and cost.

Key Responsibilities

1. DFT Architecture & Strategy: Define and implement DFT architecture at block/IP or SoC level. Specify test methodologies (scan, MBIST, boundary scan, compression). Ensure testability is built early into the RTL design flow. Balance trade-offs between coverage, area, power, and test time.
2. DFT Implementation: Perform scan insertion and stitching. Generate and simulate ATPG patterns. Integrate MBIST / LBIST / boundary scan. Develop and validate DFT timing constraints (STA). Execute DFT flows at RTL and gate level.
3. Test Coverage & Quality: Analyze and improve fault coverage. Debug scan/ATPG issues and resolve coverage holes. Optimize pattern count, test cost, and test time.
4. Verification & Signoff: Run DFT verification and DRC checks. Ensure clean DFT signoff, including coverage, timing, and power impact. Validate patterns using simulation and test tools. Support DFT integration guidelines at SoC level.
5. Cross-Functional Collaboration: Work with RTL Design, Physical Design (PD), Verification, and Test Engineering / ATE. Drive issue resolution across teams and ensure end-to-end execution of DFT flows.
6. Silicon Bring-up & Debug: Support post-silicon debug and yield improvement. Debug tester failures and improve manufacturing coverage. Assist customer or product teams during bring-up.

Required Skills & Expertise

Core Technical Skills Strong expertise in scan insertion and compression, ATPG and fault models, MBIST / LBIST, JTAG / Boundary Scan (IEEE 1149.1), RTL design and verification, STA and timing closure, and SoC design flow. Familiarity with tools such as Synopsys / Cadence / Siemens tools (e.g., TestMAX, Tessent, Modus), simulation tools (VCS, etc.), and scripting languages (TCL, Python, Perl) is essential. A BSEE/MSEE or equivalent is typically required, along with proven experience in end-to-end DFT implementation and debugging.