Dft Design Engineer

Randstad; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Randstad invites a DFT engineer to join our semiconductor test team in Bengaluru. The role emphasizes BSCAN, MBIST, SCAN and ATPG concepts, with hands-on work in pattern generation, simulations and debugging using Cadence, Synopsys and related tools.

You will collaborate with cross-functional teams and mentor junior DFT engineers through post-silicon bring-up and production activities. Strong communication and analytical skills are essential as you help improve scan test coverage and provide

Qualifications

• Clear understanding of BSCAN, MBIST, SCAN, ATPG and simulation concepts.
• Experience in MBIST insertion, Scan Insertion, ATPG pattern generation and simulations.
• Exposure to tester debugging using shmoo plots and graphs.

Responsibilities

• Lead DFT activities across cross-functional and customer teams.
• Provide test mode timing constraints to STA and PD teams.
• Post-silicon bring-up and production activities support.

Skills

BSCAN concepts

MBIST concepts

SCAN concepts

ATPG concepts

ATPG pattern generation

Simulation concepts

MBIST insertion

Scan insertion

ATPG simulations

Debugging skills

Cross-functional comms

Mentoring DFT engineers

Timing analysis

Tools

Cadence Tessent

Siemens Tessent

Synopsys tools

VCS

NCSim

Xcelium

Job description

Role

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.


• Should have experience in atleast one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.


• Good to have worked on zero delay as well as SDF Timing Simulations.


• Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.


• Good to have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.


• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.


• The candidate should have experience of providing test mode timing constraints to STA and PD teams.

Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.

Client Description

Overview

It is a trusted company which satisfied major clients in the semiconductor market. Established in 2017, headquartered in India, We are committed to attracting and developing a diverse workforce of DFT professionals that share the common value of collaboration. We believe in teaming together with our clients to see beyond the surface of changes and problems organizations face in this fast changing world to discover opportunities others might miss and face the future with greater confidence.