DFT Engineer // DEFT SEMICONDUCTORS // 3-15 Yrs // Bangalore

2coms; Bengaluru Urban; Hybrid; INR 1,200,000 - 2,400,000; Full time

Job summary

DeFT Semiconductors is seeking a DFT engineer to work on BSCAN/MBIST/ATPG, simulation and debugging of SoC-level DFT flows in Bangalore. The role involves interfacing with STA/PD teams and post-silicon activities, with exposure to industry standard tools.

Ideal candidates have hands-on experience with zero-delay and SDF timing simulations, fault models, and debug using GUI simulators. Office-based with hybrid/remote options based on project needs.

Qualifications

• Zero-delay and SDF timing simulations experience.
• Strong debugging with GUI simulators (VCS, NCSim, Xcelium).
• Experience with fault models: stuck-at, TDF, IDDQ.
• SoC-level DFT with OCC/OPCG insertion and clock handling.
• Knowledge of test mode timing constraints to STA and PD teams.

Skills

BSCAN

MBIST

SCAN

ATPG

Simulation

Debugging

DFT expertise

Test mode timing

Tools

Cadence

Siemens Tessent

Synopsys

Job description

Bangalore North, India

Job Description

About the company:

DeFT Semiconductors is a trusted company which satisfied major clients in the semiconductor market. Established in 2017, headquartered in India, We are committed to attracting and developing a diverse workforce of DFT professionals that share the common value of collaboration. We believe in teaming together with our clients to see beyond the surface of changes and problems organizations face in this fast changing world to discover opportunities others might miss and face the future with greater confidence.

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
  
• Should have experience in atleast one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
  
• Good to have worked on zero delay as well as SDF Timing Simulations.
  
• Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
  
• Good to have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
  
• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
  
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.
  

Requirements

Q1. Does candidate have experience in zero delay as well as SDF Timing Simulations?

Q2. What is the notice period ?

Q3. Do you have hands-on experience in the DFT (Design for Testability) segment ?

Q4. Are you comfortable working from an office location, with flexibility for hybrid or remote arrangements based on project requirements ?

Q5. Which of the following DFT concepts do you have practical experience with? * BSCAN

MBIST

SCAN

ATPG Simulation
Q6. How many years of experience do you have in the DFT segment?

Q7. Is the candidate ready to relocate and work from Banaglore?