Design Verification Engineer

Sevya Multimedia; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Job summary

Sevya Multimedia seeks experienced verification engineers to validate an IP/full-chip using SystemVerilog/UVM. The role requires expertise in PCIe/DDR verification, and hands-on work with Cadence/Mentor/Synopsys toolchains and Verilator.

You will contribute to test planning, constraint-based random verification, and coverage strategies while collaborating with cross-functional teams in a fast-paced environment.

Qualifications

• 3+ years of industry experience in Design Verification using System-Verilog/UVM.
• Strong understanding of Digital Design and Verification methodologies.
• Experience in SystemVerilog/UVM-based IP/SoC verification.
• Knowledge of constraint-based random verification and coverage metrics.

Responsibilities

• Verify IP/full-chip using SystemVerilog/UVM in a PCIe/DDR environment.
• Develop and execute test plans and test cases; implement VIPs as needed.
• Utilize Verilator and industry-standard EDA tools for simulation and verification.
• Collaborate with design teams, document results, and drive coverage closure.

Skills

SystemVerilog/UVM

PCIe/DDR verification

Digital design & verification

Constrained random verification

VIP coding & test plans

Coverage strategies

Unix/Linux scripting (Shell/Python)

Interpersonal communication

Tools

Cadence Mentor Synopsys

Verilator

Job description

We need experienced engineers to verify an IP/full-chip using System Verilog/UVM. Expertise in PCIe/DDR verification is preferable at IP/chip level.

Skills

• Overall 3+ years industry experience in Design Verification using System-Verilog/C/UVM.
• Generic knowhow on Digital Design and Verification methodologies.
• Experience in System Verilog/UVM based IP/SoC verification using advanced technologies.
• Good understanding of Constraint based Random verification; VIP coding; Test Plan design; Test cases coding; Coverage strategies and measurement
• Proficient in EDA tools used for Design Verification (e.g. Cadence/Mentor/Synopsys simulation suites; Verilator).
• Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
• Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills

Traits

• Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
• Solutions orientation; Quality driven; Execution minded