Design Verification Engineer

Cadence; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cadence in India is seeking a highly motivated verification engineer specialized in VIP development and functional verification. The role involves designing, verifying and deploying VIP, with close collaboration across cross-functional teams and customers.

Ideal candidates will have 3-6 years of design verification experience, strong SV/UVM-based test environment skills, and hands-on knowledge of C/C++/scripting, plus familiarity with PCIe, Ethernet, UCIe and CXL UAlink protocols.

Qualifications

• 3-6 years of design verification.
• Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills.
• Hands-on knowledge of C/C++/Scripting.
• Working experience on layered Protocols - PCIe, Ethernet, UCIe, CXL UAlink.
• Prior VIP usage and development experience is a plus.
• Strong Digital Electronics and Programming fundamentals.
• Self-motivated with strong analytical and communication skills.

Responsibilities

• Responsible for the design, development, verification and deployment of the VIP

Skills

Functional verification

Test environment creation

C/C++/Scripting

Analytical skills

Communication skills

Tools

SV/UVM

VIP usage/development

Job description

We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers.

Job Responsibilities

Responsible for the design, development, verification and deployment of the VIP

.

Experience and Technical Skills required

• 3- 6 years of design verification.
• Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills.
• Hands-on knowledge of C/C++/Scripting
• Working experience on layered Protocols - PCIe, Ethernet, UCIe, CXL UAlink.
• Prior VIP usage and development experience is a plus
• Strong Digital Electronics and Programming fundamental
• Self-motivated individuals with strong analytical and communication skills.