Design Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an experienced Verification Engineer to lead advanced IP/SoC verification using UVM and SystemVerilog. The role requires hands-on development of testbenches and coverage-driven methodologies across CPU, GPU, and high-speed protocols.

You will work closely with RTL designers and validation teams, executing gate level simulations as needed and ensuring regression, flagging issues, and sign-off readiness throughout the product lifecycle.

Qualifications

• Hands-on experience with UVM/SystemVerilog verification environments.
• Deep protocol knowledge across CPU, GPU, Ethernet, MIPI, PCIe, CXL, UCIe and SoC interconnects.
• Experience with functional coverage, assertions (SVA) and constrained-random verification.

Responsibilities

• Develop and execute verification plans for complex IPs and SoCs.
• Design, develop, and maintain UVM/SystemVerilog verification environments.
• Create reusable testbenches, sequences, scoreboards, monitors and checkers.
• Perform functional, code, and assertion coverage analysis.
• Debug RTL and verification environment issues.
• Execute Gate Level Simulation (GLS) and resolve timing issues.
• Verify PCIe, CXL, UCIe, Ethernet, MIPI, Cache Coherency and SoC interconnects.
• Collaborate with RTL designers and validation teams through the lifecycle.
• Support regression, coverage closure and verification sign-off activities.

Skills

SystemVerilog

UVM

GLS

PCIe

CXL

UCIe

Ethernet

MIPI

Cache Coherency

SoC Interconnects

UPF/CPF

Python scripting

Perl scripting

Shell scripting

EDA tools

Debugging skills

Education

Bachelor's or Master's degree in Electronics / Electrical / Computer Engineering

Tools

Synopsys tools

Cadence tools

Siemens EDA tools

Job description

Job Title: Verification Engineer (CPU/GPU/SoC & High Speed Protocol Verification)

• Experience 5–18 Years
• Notice Period-Immediate Joiners to 30 Days Only

Job Summary

We are looking for experienced Verification Engineers with strong expertise in SoC/IP verification and industry-standard protocols. The ideal candidate should have hands‑on experience in UVM/SystemVerilog‑based verification environments and deep protocol knowledge in one or more of the following domains: CPU, GPU, Ethernet, GLS, Cache, MIPI, SoC, UCIe, PCIe, CXL, and Low Power Verification.

Key Responsibilities

• Develop and execute verification plans for complex IPs and SoCs.
• Design, develop, and maintain UVM/SystemVerilog verification environments.
• Create reusable testbenches, sequences, scoreboards, monitors, and checkers.
• Perform functional, code, and assertion coverage analysis.
• Debug RTL and verification environment issues.
• Execute Gate Level Simulation (GLS) and resolve timing‑related issues.
• Verify industry‑standard protocols such as PCIe, CXL, UCIe, Ethernet, MIPI, Cache Coherency, CPU, GPU, and SoC interconnects.
• Collaborate with RTL designers, architects, and validation teams throughout the product lifecycle.
• Support regression, coverage closure, and verification sign‑off activities.

Required Skills

• Strong experience in SystemVerilog and UVM.
• Expertise in one or more protocols:
• Ethernet
• Gate Level Simulation (GLS)
• Cache Coherency
• MIPI
• CXL
• Low Power Verification (UPF/CPF)
• Strong debugging and problem‑solving skills.
• Experience with functional coverage, assertions (SVA), and constrained‑random verification.
• Familiarity with scripting languages such as Python, Perl, or Shell is preferred.
• Experience with industry‑standard EDA tools from Synopsys, Cadence, or Siemens EDA is an advantage.

Preferred Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Excellent communication and teamwork skills.
• Ability to work in a fast‑paced semiconductor product development environment.
• Experience: 5–18 Years
• Notice Period: Immediate to 30 Days Only