Design Verification Engineer

Proxelera; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Proxelera in Bengaluru is seeking a Design Verification Engineer with 5+ years experience to design and verify SoCs for data center applications.

You will work on IP/SoC verification plans, UVM-based testbenches, and closure from test-planning to verification closure, using Verilog, SystemVerilog, UVM, and Python.

Experience in RDMA, PCIe, Ethernet interfaces is a plus; join a dynamic team building innovative ASIC solutions.

Qualifications

• 5+ years of experience in Design Verification for SoCs.
• Hands-on verification with UVM/OVM methodologies.
• Experience with IP/sub-system or SoC verification in data center ASICs.

Responsibilities

• Perform test-planning, develop UVM-based testbenches, and drive verification closure.
• Define and implement IP/SoC verification plans for data-center projects.
• Develop functional tests based on the verification plan.
• Contribute to RTL-to-test integration and debug using Verilog/SystemVerilog.

Skills

Verilog

SystemVerilog

UVM

C/C++

Python

Job description

Join Proxelera- Innovate the future of VLSI

If you're looking for a place where you can innovate freely, grow fast, and contribute to something future-facing - Proxelera might just be your next big move.

Job Title: DV Engineers (Ethernet and PCIE)

Experience: 5+yrs

• We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for data center applications.
• You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure.
• Networking Responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan.
• Hands-on experience in Verilog, SystemVerilog, UVM , C/C, Python based verification Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
• Experience in one or more of the following areas along with functional verification - RDMA, PCIe, SRIO & Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etc
• Experience in development of UVM based verification environments from scratch